An Overlaying Technique for Solving Linear Equations in Real-Time Computing
A computer organization for solving a continuous stream of sets of linear equations A*b with relatively close consecutive parameters is described. The conditions of closeness enabling this technique are monitored during the computations. The cycles of ...
A Clustered Failure Model for the Memory Array Reconfiguration Problem
Reconfiguration of memory array using spare rows and spare columns, which has been shown to be a useful technique for yield enhancement of memories, is considered. A clustered failure model that adopts the center-satellite approach of F.J. Meyer and ...
An Iteration Partition Approach for Cache or Local Memory Thrashing on Parallel Processing
Parallel processing systems with cache or local memory in the memory hierarchies are considered. These systems have a local cache memory in each processor and usually employ a write-invalidate protocol for the cache coherence. In such systems, a problem ...
Some Codes for Correcting and Detecting Unidirectional Byte Errors
Codes for correcting and detecting unidirectional byte errors are investigated. The relations between distances and the error-correcting and -detecting capabilities of such codes are derived. It is shown that a two-fold unidirectional b-bit-byte error-...
Availability of k-Coterie
The distributed k-mutual-exclusion problem (k-mutex problem) is the problem of guaranteeing that at most k processes at a time can enter a critical section at a time in a distribution system. A method proposed for the solution of the distributed mutual ...
Rearrangeable Three-Stage Interconnection Networks and Their Routing Properties
A rearrangeable network is an interconnection network which can achieve all possible permutations of its inputs' connections to its outputs. One class of rearrangeable networks, which have been studied are Clos three-stage networks. Earlier procedures ...
Minimization of AND-EXOR Expressions Using Rewrite Rules
Conditions for generating optimal two-level AND-EXOR representations using rewrite rules are considered. Four results are presented. First, it is shown that a necessary condition for obtaining minimality is a temporary increase in the size of ...
Time-Division Optical Communications in Multiprocessor Arrays
An optical communication structure is proposed for multiprocessor arrays which exploits the high communication bandwidth of optical waveguides. The structure takes advantage of two properties of optical signal transmissions on waveguides, namely, ...
Solution of Switching Equations Based on a Tabular Algebra
Several problems in switching theory such as automatic test pattern generation, can be exactly and elegantly investigated by using switching equations. An efficient tabular method is presented to solve these switching equations. The solutions of a given ...
Optimal Joining of Compacted Cells
Three algorithms to join two compacted cells by using a combination of stretching and river routing are developed. Each of these obtains the minimum area joining. One algorithm obtains a minimum area joining that also minimizes the length of the longest ...
A New Technique for Fast Number Comparison in the Residue Number System
A technique for number comparison in the residue number system is presented, and its theoretical validity is proved. The proposed solution is based on using a diagonal function to obtain a magnitude order of the numbers. In a first approach the function ...
Line Digraph Iterations and Connectivity Analysis of de Bruijn and Kautz Graphs
A graph has spread (m, k, l) if for any m+1 distinct nodes x, y/sub 1/, . . ., y/sub m/ and m positive integers r/sub 1/, . . ., r/sub m/, such that Sigma /sub i/r/sub i/=k, there exist k node-disjoint paths of length at most 1 from x to the y/sub i/, ...
Analytical Estimation of Vector Access Performance in Parallel Memory Architectures
A limiting factor in high-performance vector computers is the rate at which data can be moved to and from memory during vector loads and stores. To increase the bandwidth of vector memory operations, several investigators have proposed the use of ...
A Note on Orthogonal Graphs
Orthogonal graphs are natural extensions of the classical binary and b-ary hypercubes b=2/sup l/ and are abstractions of interconnection schemes used for conflict-free orthogonal memory access in multiprocessor design. Based on the type of connection ...
Improved Bounds for Algorithm-Based Fault Tolerance
Lower and upper bounds are established for the combinatorial problem of constructing minimal test sets for error detection in multiprocessor systems. The construction for detecting two errors produces minimal test sets, while that for three errors ...
Corrigendum to "Synthetic Traces for Trace-Driven Simulation of Cache Memories"
Three errors appearing in the above-tilted paper by D. Thiebaut, J. Wolf, and H. Stone are corrected. They were introduced during the revision process and do not affect the results.
A Neuron-Weighted Learning Algorithm and its Hardware Implementation in Associative Memories
A novel learning algorithm for a neuron-weighted associative memory (NWAM) is presented. The learning procedure is cast as a global minimization, solved by a gradient descent rule. An analog neural network for implementing the learning method is ...
