research-article

A Systolic Power-Sum Circuit for GF(2/sup m/)

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Shyue-Win WeiAuthors Info & Claims

IEEE Transactions on Computers, Volume 43, Issue 2

Pages 226 - 229

https://doi.org/10.1109/12.262128

Published: 01 February 1994 Publication History

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Abstract

A systolic power-sum circuit designed to perform AB/sup 2/+C computations in the finite field GF(2/sup m/) is presented, where A, B, and C are arbitrary elements of GF(2/sup m/). This new circuit is constructed by m/sup 2/ identical cells, each of which consists of three 2-input AND logical gates, one 2-input XOR gate, one 3-input XOR gate, and ten latches. The AB/sup 2/+C computation is required in decoding many error-correcting codes. The paper shows that a decoder implemented using the new power-sum circuit will have less complex circuitry and shorter decoding delay than one implemented using conventional product-sum multipliers.

References

[1]

{1} R. E. Blahut, Theory and Practice of Error Control Codes. Reading, MA: Addison-Wesley, 1983.

Google Scholar

[2]

{2} A. M. Michelson and A. H. Levesque, Error-Control Techniques for Digital Communication. New York: Wiley, 1985.

Google Scholar

[3]

{3} S. Lin and D. J. Costellor, Jr., Error Control Coding. Englewood Cliffs, NJ: Prentice-Hall, 1983.

Digital Library

Google Scholar

[4]

{4} H. M. Shao and I. S. Reed, "On the VLSI design of a pipeline Reed-Solomon decoder using systolic arrays," IEEE Trans. Comput., vol. C-37, pp. 1273-1280, 1988.

Digital Library

Google Scholar

[5]

{5} H. Okano and H. Imai, "A construction method of high-speed decoders using ROM's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon codes," IEEE Trans. Comput., vol. C-36, pp. 1165-1171, 1987.

Digital Library

Google Scholar

[6]

{6} C.-L. Wang and W.-J. Bair, "A VLSI architecture for implementation of the decoder for binary BCH codes," in Proc. Symp. Commun., TAiwan, Dec. 9-13, 1991, pp. 36-40.

Google Scholar

[7]

{7} S. W. Wei and C. H. Wei, "High speed decoder of Reed-Solomon codes," IEEE Trans. Commun., to appear.

Google Scholar

[8]

{8} E. R. Berlekamp, "Bit-serial Reed-Solomon encoders," IEEE Trans. Inform Theory, vol. IT-28, pp. 869-874, 1982.

Google Scholar

[9]

{9} C. C. Wang et al., "VLSI architectures for computing multiplications and inverses in GF(2m), IEEE Trans. Comput., vol. C-34, pp. 709-716, 1985.

Digital Library

Google Scholar

[10]

{10} C.-S. Yeh, S. Reed, and T. K. Truong, "Systolic multipliers for finite fields GF(2m), IEEE Trans. Comput., vol. C-33, pp. 357-360, 1984.

Google Scholar

[11]

{11} B. A. Laws, Jr. and C. K. Rushforth, "A cellular-array multiplier for GF(2m), IEEE Trans. Comput., vol. C-20, pp. 1573-1578, 1971.

Google Scholar

[12]

{12} C.-L. Wang and J.-L. Lin, "Systolic array implementation of multipliers for finite fields GF(2m), IEEE Trans. Circuits Syst., vol. CAS-38, pp. 796-800, 1991.

Google Scholar

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Lee HKim TKim KMezhuyev VBenedicenti L(2017)Efficient montgomery AB2 multiplier for finite fields defined by irreducible all-one polynomialsProceedings of the 6th International Conference on Software and Computer Applications10.1145/3056662.3056676(218-222)Online publication date: 26-Feb-2017
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Kim HLee S(2009)Area and time efficient AB2 multipliers based on cellular automataComputer Standards & Interfaces10.1016/j.csi.2007.11.01531:1(137-143)Online publication date: 1-Jan-2009
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Lee CChen YChiou CLin J(2007)Unified parallel systolic multiplier over GF(2m)Journal of Computer Science and Technology10.1007/s11390-007-9003-022:1(28-38)Online publication date: 1-Jan-2007
https://dl.acm.org/doi/10.1007/s11390-007-9003-0
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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 43, Issue 2

February 1994

135 pages

ISSN:0018-9340

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IEEE Computer Society

United States

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Published: 01 February 1994

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Lee HKim TKim KMezhuyev VBenedicenti L(2017)Efficient montgomery AB2 multiplier for finite fields defined by irreducible all-one polynomialsProceedings of the 6th International Conference on Software and Computer Applications10.1145/3056662.3056676(218-222)Online publication date: 26-Feb-2017
https://dl.acm.org/doi/10.1145/3056662.3056676
Kim HLee S(2009)Area and time efficient AB2 multipliers based on cellular automataComputer Standards & Interfaces10.1016/j.csi.2007.11.01531:1(137-143)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1016/j.csi.2007.11.015
Lee CChen YChiou CLin J(2007)Unified parallel systolic multiplier over GF(2m)Journal of Computer Science and Technology10.1007/s11390-007-9003-022:1(28-38)Online publication date: 1-Jan-2007
https://dl.acm.org/doi/10.1007/s11390-007-9003-0
Lee CHorng JJou I(2006)Low-complexity bit-parallel multiplier over GF(2m) using dual basis representationJournal of Computer Science and Technology10.1007/s11390-006-0887-x21:6(887-892)Online publication date: 1-Nov-2006
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Ting YLu ELee J(2004)Low complexity bit-parallel systolic architecture for computing C + AB2 over a class of GF(2)Integration, the VLSI Journal10.1016/j.vlsi.2004.01.00337:3(167-176)Online publication date: 1-Aug-2004
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Jeon JYoo K(2003)Computational algorithm and architecture for AB2 multiplication in finite fieldsProceedings of the 2003 international conference on Computational science and its applications: PartI10.5555/1756748.1756858(947-956)Online publication date: 18-May-2003
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Lee WHeo YYoo K(2003)Efficient architecture for exponentiation and division in GF(2m) using irreducible AOPProceedings of the 2003 international conference on Computational science and its applications: PartI10.5555/1756748.1756851(883-892)Online publication date: 18-May-2003
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Kim NKho DYoo K(2002)Inversion/Division Systolic Architecture for Public-Key Cryptosystems in GF(2m)Proceedings of the 5th International Conference on Information Security10.5555/648026.744520(289-299)Online publication date: 30-Sep-2002
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Kim NLee WYoo K(2002)Efficient Power-Sum Systolic Architectures for Public-Key Cryptosystems in GF(2m)Proceedings of the 8th Annual International Conference on Computing and Combinatorics10.5555/646720.702408(153-161)Online publication date: 15-Aug-2002
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Kim NKim HLee WYoo K(2002)A Power-Sum Systolic Architecture in GF(2m)Revised Papers from the International Conference on Information Networking, Wireless Communications Technologies and Network Applications-Part II10.5555/646286.688311(409-417)Online publication date: 30-Jan-2002
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