research-article

Fault-Tolerant FFT Networks

Authors:

Jacob A. AbrahamAuthors Info & Claims

IEEE Transactions on Computers, Volume 37, Issue 5

Pages 548 - 561

https://doi.org/10.1109/12.4606

Published: 01 May 1988 Publication History

Abstract

Two concurrent error detection (CED) schemes are proposed for N-point fast Fourier transform (FFT) networks that consists of log/sub 2/N stages with N/2 two-point butterfly modules for each stage. The method assumes that failures are confined to a single complex multiplier or adder or to one input or output set of lines. Such a fault model covers a broad class of faults. It is shown that only a small overhead ratio, O(2/log/sub 2/N) of hardware, is required for the networks to obtain fault-secure results in the first scheme. A novel data retry technique is used to locate the faulty modules. Large roundoff errors can be detected and treated in the same manner as functional errors. The retry technique can also distinguish between the roundoff errors and functional errors that are caused by some physical failures. In the second scheme, a time-redundancy method is used to achieve both error detection and location. It is sown that only negligible hardware overhead is required. However, the throughput is reduced to half that of the original system, without both error detection and location, because of the nature of time-redundancy methods.

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https://dl.acm.org/doi/10.1109/LES.2022.3212776
Hui ZWang YQin TTang HWang H(2018)Optimized Software-Based Hardening Strategies for Matrix Multiplication and Fast Fourier TransformProceedings of the 2nd International Conference on Algorithms, Computing and Systems10.1145/3242840.3242846(127-132)Online publication date: 27-Jul-2018
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Liang XChen JTao DLi SWu PLi HOuyang KLiu YSong FChen ZMohr BRaghavan P(2017)Correcting soft errors online in fast fourier transformProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/3126908.3126915(1-12)Online publication date: 12-Nov-2017
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Fault-Tolerant FFT Networks

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 37, Issue 5

May 1988

133 pages

ISSN:0018-9340

Editor:
Bruce D. Shriver

Issue’s Table of Contents

Copyright © Copyright © 1988 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 May 1988

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Cited By

Safarpour MSilvén O(2023)LoFFT: Low-Voltage FFT Using Lightweight Fault Detection for Energy EfficiencyIEEE Embedded Systems Letters10.1109/LES.2022.321277615:3(125-128)Online publication date: 1-Sep-2023
https://dl.acm.org/doi/10.1109/LES.2022.3212776
Hui ZWang YQin TTang HWang H(2018)Optimized Software-Based Hardening Strategies for Matrix Multiplication and Fast Fourier TransformProceedings of the 2nd International Conference on Algorithms, Computing and Systems10.1145/3242840.3242846(127-132)Online publication date: 27-Jul-2018
https://dl.acm.org/doi/10.1145/3242840.3242846
Liang XChen JTao DLi SWu PLi HOuyang KLiu YSong FChen ZMohr BRaghavan P(2017)Correcting soft errors online in fast fourier transformProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.1145/3126908.3126915(1-12)Online publication date: 12-Nov-2017
https://dl.acm.org/doi/10.1145/3126908.3126915
Yu QMaddah-Ali MAvestimehr A(2017)Coded fourier transform2017 55th Annual Allerton Conference on Communication, Control, and Computing (Allerton)10.1109/ALLERTON.2017.8262778(494-501)Online publication date: 3-Oct-2017
https://dl.acm.org/doi/10.1109/ALLERTON.2017.8262778
Li TAmbrose JRagel RParameswaran S(2016)Processor Design for Soft ErrorsACM Computing Surveys10.1145/299635749:3(1-44)Online publication date: 8-Nov-2016
https://dl.acm.org/doi/10.1145/2996357
Gao ZReviriego PXu ZSu XZhao MWang JMaestro J(2016)Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval ChecksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.240862124:2(769-773)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2408621
Wu TGanesan KHu YWong HWong SMitra S(2016)TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.247437335:4(521-534)Online publication date: 1-Apr-2016
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de Oliveira DPilla LLunardi CCarro LNavaux PRech PDeBardeleben NDeBardeleben NCappello FClay R(2015)The Path to ExascaleProceedings of the 5th Workshop on Fault Tolerance for HPC at eXtreme Scale10.1145/2751504.2751510(55-62)Online publication date: 15-Jun-2015
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Sengupta ABhadauria S(2015)Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesisExpert Systems with Applications: An International Journal10.1016/j.eswa.2015.01.05842:10(4719-4732)Online publication date: 15-Jun-2015
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Sengupta ABhadauria S(2015)Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computingAdvances in Engineering Software10.1016/j.advengsoft.2014.12.00882:C(14-24)Online publication date: 1-Apr-2015
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