research-article

Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns

Authors:

Jerry TyszerAuthors Info & Claims

IEEE Transactions on Computers, Volume 45, Issue 8

Pages 939 - 949

https://doi.org/10.1109/12.536236

Published: 01 August 1996 Publication History

Abstract

Existing built-in self-test (BIST) strategies require the use of specialized test pattern generation hardware which introduces significant area overhead and performance degradation. In this paper, we propose an entirely new approach to generate test patterns. The method is based on adders widely available in data-path architectures used in digital signal processing circuits and general purpose processors. The resultant test patterns, generated by continuously accumulating a constant value, provide a complete state coverage on subspaces of contiguous bits. This new test generation scheme, along with the recently introduced accumulator-based compaction scheme [19] facilitates a BIST strategy for high performance datapath architectures that uses the functionality of existing hardware, is entirely integrated with the circuit under test, and results in at-speed testing with no performance degradation and no area overhead.

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Cited By

Voyiatzis IEfstathiou CPatriarcheas K(2016)Software-based SIC pair GenerationProceedings of the 20th Pan-Hellenic Conference on Informatics10.1145/3003733.3003803(1-6)Online publication date: 10-Nov-2016
https://dl.acm.org/doi/10.1145/3003733.3003803
Voyiatzis IEfstathiou CGeorge GStefanos GLazaros MPanagiotis TCleo S(2015)Accumulator-based generation for serial TPGProceedings of the 19th Panhellenic Conference on Informatics10.1145/2801948.2801969(426-430)Online publication date: 1-Oct-2015
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Mrozek IYarmolik V(2012)Antirandom Test Vectors for BIST in Hardware/Software SystemsFundamenta Informaticae10.5555/2385135.2385138119:2(163-185)Online publication date: 1-Apr-2012
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Index Terms

Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
1. Hardware

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 45, Issue 8

August 1996

129 pages

ISSN:0018-9340

Editor:
Jane W. S. Liu
Univ. of Illinois, Urbana

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Copyright © Copyright © 1996 IEEE. All Rights Reserved.

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IEEE Computer Society

United States

Publication History

Published: 01 August 1996

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Voyiatzis IEfstathiou CPatriarcheas K(2016)Software-based SIC pair GenerationProceedings of the 20th Pan-Hellenic Conference on Informatics10.1145/3003733.3003803(1-6)Online publication date: 10-Nov-2016
https://dl.acm.org/doi/10.1145/3003733.3003803
Voyiatzis IEfstathiou CGeorge GStefanos GLazaros MPanagiotis TCleo S(2015)Accumulator-based generation for serial TPGProceedings of the 19th Panhellenic Conference on Informatics10.1145/2801948.2801969(426-430)Online publication date: 1-Oct-2015
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Mrozek IYarmolik V(2012)Iterative Antirandom TestingJournal of Electronic Testing: Theory and Applications10.1007/s10836-011-5272-128:3(301-315)Online publication date: 1-Jun-2012
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Kim YKim KKim ISon HKang S(2008)A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BISTIEICE - Transactions on Information and Systems10.1093/ietisy/e91-d.4.1185E91-D:4(1185-1188)Online publication date: 1-Apr-2008
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