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Verification Testing A Pseudoexhaustive Test Technique

Published: 01 June 1984 Publication History
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  • Abstract

    A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present day automatic test pattern generation (ATPG) programs. Fault simulation or fault modeling is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher all irredundant multiple as well as single stuck faults are detected. The test patterns are easily generated algorithmically either by program or hardware.

    References

    [1]
    P. H. Bardell and W. H. McAnney, "A view from the trenches: Production testing of a family of VLSI multichip modules," in Proc. 11th Annu. Int. Symp. Fault-Tolerant Computing, Portland, ME, June 24-26, 1981, pp. 281-283.
    [2]
    Z. Barzilai, J. Savir, G. Markowsky, and M. Smith, "The weighted syndrome sums approach to VLSI testing," IEEE Trans. Comput., vol. C-30, pp. 996-1000, Dec. 1981.
    [3]
    Z. Barzilai, D. Coppersmith, and A. L. Rosenberg, "Exhaustive generation of bit patterns with applications to VLSI self-testing," IEEE Trans. Comput., vol. C-32, pp. 190-194, Feb. 1983.
    [4]
    N. Benowitz, D. F. Calhoun, G. E. Alderson, J. E. Bauer, and C. T. Joeckel, "An advanced fault isolation system for digital logic," IEEE Trans. Comput., vol. C-24, pp. 489-497, May 1975.
    [5]
    W. C. Carter, "The ubiquitous parity bit," in Proc. 12th Annu. Int. Symp. Fault-Tolerant Computing, Santa Monica, CA, June 22-24, 1982, pp. 289-296.
    [6]
    E. B. Eichelberger and T. W. Williams, "A logic design structure for LSI testability," in Proc. 14th Annu. Design Automat. Conf., New Orleans, LA, June 20-22, 1977, pp. 462-468; see also, Proc. 15th Annu. Design Automat. Conf., May 1978.
    [7]
    E. B. Eichelberger and E. Lindbloom, "Random-pattern coverage enhancement and diagnosis for LSSD logic self-test," IBM J. Res. Develop., vol. 27, no. 3, pp. 265-272, May 1983.
    [8]
    F. Hirose and V. Singh, "McDDP, A program for partitioning verification testing matrices," Center for Reliable Computing, Stanford Univ., Stanford, CA, Tech. Rep. 81-13, July 1982.
    [9]
    M. Ichikawa, "Constant weight code generators," Center for Reliable Computing, Stanford Univ., Stanford, CA, Tech. Rep. 82-7, June 1982.
    [10]
    E. J. McCluskey and S. Bozorgui-Nesbat, "Design for autonomous test," IEEE Trans. Comput., vol. C-30, pp. 866-875, Nov. 1981.
    [11]
    E. J. McCluskey, "Verification testing," in Proc. 19th Annu. Design Automat. Conf., Las Vegas, NV, June 14-16, 1982, pp. 495-500.
    [12]
    E. J. McCluskey, "Built-in verification test," in Proc. 1982 IEEE Test Conf., Philadelphia, PA, Nov. 11-13, 1982, pp. 183-190.
    [13]
    E. J. McCluskey, "Design for testability," in Recent Developments in Fault-Tolerant Computing, D. K. Pradham, Ed. Englewood Cliffs, NJ: Prentice-Hall, 1984.
    [14]
    J. Savir, G. Ditlow, and P. H. Bardell, "Random pattern testability," in Proc. 13th Annu. int. Symp. Fault-Tolerant Computing, Milan, Italy, June 28-30, 1983, pp. 80-89.
    [15]
    D. T. Tang and L. S. Woo, "Exhaustive test pattern generation with constant weight vectors," IEEE Trans. Comput., vol. C-32, pp. 1145-1150, Dec. 1983.
    [16]
    J. T. Tang and C. L. Chen, "Logic test pattern generation using linear codes," in Proc. 13th Annu. Int. Symp. Fault-Tolerant Computing, Milan, Italy, June 28-30, 1983, pp. 222-226.
    [17]
    L. -T. Wang, "A new condensed linear feedback shift register designed for VLSI/system testing," in Proc. 14th Annu. Int. Symp. Fault Tolerant Computing, Orlando, FL, June 20-22, 1984.
    [18]
    T. W. Williams and K. P. Parker, "Design for testability--A survey," Proc. IEEE, vol. 71, pp. 98-112, Jan. 1983.

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    • (2005)Concurrent Online Testing of Identical Circuits Using Nonidentical Input VectorsIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2005.302:3(190-200)Online publication date: 1-Jul-2005
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        Published In

        cover image IEEE Transactions on Computers
        IEEE Transactions on Computers  Volume 33, Issue 6
        June 1984
        134 pages

        Publisher

        IEEE Computer Society

        United States

        Publication History

        Published: 01 June 1984

        Author Tags

        1. Autonomous test
        2. built-in self-test
        3. pseudoexhaustive test
        4. test pattern generation

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        • (2008)CASPProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403590(885-890)Online publication date: 10-Mar-2008
        • (2006)VLSI Test Principles and ArchitecturesundefinedOnline publication date: 14-Aug-2006
        • (2005)Concurrent Online Testing of Identical Circuits Using Nonidentical Input VectorsIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2005.302:3(190-200)Online publication date: 1-Jul-2005
        • (2004)Path sensitization and sub-circuit partition of CUT using t,-distribution for pseudo-exhaustive testingProceedings of the Third Asian simulation conference on Systems Modeling and Simulation: theory and applications10.1007/978-3-540-30585-9_23(205-213)Online publication date: 4-Oct-2004
        • (2003)Design Of A Universal BIST (UBIST) StructureProceedings of the 16th International Conference on VLSI Design10.5555/832285.835569Online publication date: 4-Jan-2003
        • (2003)A BIST Pattern Generator Design for Near-Perfect Fault CoverageIEEE Transactions on Computers10.1109/TC.2003.125285152:12(1543-1558)Online publication date: 1-Dec-2003
        • (2002)High Defect Coverage with Low-Power Test Sequences in a BIST EnvironmentIEEE Design & Test10.1109/MDT.2002.103379119:5(44-52)Online publication date: 1-Sep-2002
        • (2001)TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BISTProceedings of the 2001 IEEE International Test Conference10.5555/839296.843833Online publication date: 30-Oct-2001
        • (2001)Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern GeneratorIEEE Transactions on Computers10.1109/12.90899350:2(177-185)Online publication date: 1-Feb-2001
        • (2000)A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERSProceedings of the 2000 IEEE International Test Conference10.5555/839295.843625Online publication date: 3-Oct-2000
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