research-article

Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator

Authors:

Prabir Dasgupta,

Santanu Chattopadhyay,

P. Pal Chaudhuri,

Indranil SenguptaAuthors Info & Claims

IEEE Transactions on Computers, Volume 50, Issue 2

Pages 177 - 185

https://doi.org/10.1109/12.908993

Published: 01 February 2001 Publication History

Abstract

This paper presents a recursive technique for generation of pseudoexhaustive test patterns. The scheme is optimal in the sense that the first $2^k$ vectors cover all adjacent k-bit spaces exhaustively. It requires substantially lesser hardware than the existing methods and utilizes the regular, modular, and cascadable structure of local neighborhood Cellular Automata (CA), which is ideally suited for VLSI implementation. In terms of XOR gates, this approach outperforms earlier methods by 15 to 50 percent. Moreover, test effectiveness and hardware requirements have been established analytically, rather than by simple simulation and logic minimization.

References

[1]

E.J. McClusky, “Verification Testing—A Pseudoexhaustive Test Technique,” IEEE Trans. Computers, vol. 33, no. 6, pp. 541-546, June 1984.

Digital Library

[2]

D. Tang and L. Woo, “Exhaustive Test Pattern Generation with Constant Weight Vector,” IEEE Trans. Computers, vol. 32, no. 12, pp. 1145-1150, Dec. 1983.

Digital Library

[3]

L. Wang and E. McClusky, “Condensed Linear Feedback Shift Register (LFSR) Testing—A Pseudo-Exhaustive Test Technique,” IEEE Trans. Computers, vol. 35, no. 4, pp. 367-370, Apr. 1986.

Digital Library

[4]

D. Wang and C. Chen, “Logic Test Pattern Generation Using Linear Codes,” IEEE Trans. Computers, vol. 33, no. 9, pp. 845-850, Sept. 1984.

[5]

L. Wang and E. McClusky, “Circuits for Pseudo-Exhaustive Test Pattern Generation,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 1068-1080, Oct. 1988.

Digital Library

[6]

D. Wang and C. Chen, “Iterative Exhaustive Pattern Generation for Logic Testing,” IBM J. Research Development, vol. 28, pp. 212-219, Mar. 1984.

Digital Library

[7]

C. Chen, “Exhaustive Test Pattern Generation Using Cyclic Codes,” IEEE Trans. Computers, vol. 37, no. 2, pp. 225-228, Feb. 1988.

Digital Library

[8]

Z. Barzilai D. Copersmith and A. Rosenburg, “Exhaustive Generation of Bit Patterns with Application to VLSI Testing,” IEEE Trans. Computers, vol. 32,no. 2, pp. 190-194, Feb. 1983.

Digital Library

[9]

A.K. Das and P.P. Chaudhuri, “Vector Space Theoretic Analysis of Additive Cellular Automata and Its Applications for Pseudo-Exhaustive Test Pattern Generation,” IEEE Trans. Computers, vol. 42, no. 3, pp. 340-352, Mar. 1993.

Digital Library

[10]

J. Rajski and J. Tyszer, “Recursive Pseudo-Exhaustive Test Pattern Generation,” IEEE Trans. Computers, vol. 42, no. 12, pp. 1517-1521, Dec. 1993.

Digital Library

[11]

J.V. Neuman, The Theory of Self-Reproducing Automata, A.W. Burks, ed. Urbana, Ill. and London: Univ. of Illinois Press, 1966.

[12]

S. Wolfram, “Statistical Mechanics of Cellular Automata,” Review of Modern Physics, vol. 55, pp. 601-644, July 1983.

[13]

P.D. Hortensius, et al., “Cellular Automata Based Pseudo-Random Number Generators for Built-In Self-Test,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 842-859, Aug. 1989.

Digital Library

[14]

P.P. Chaudhuri D.R. Chowdhury S. Nandi and S. Chattopadhyay, Additive Cellular Automata Theory and Applications: Volume 1. IEEE CS Press, 1997.

[15]

P.D. Hortensius H.C. Card R.D. McLeod and W. Pries, “Importance Sampling for Ising Computers Using One-Dimensional Cellular Automata,” IEEE Trans. Computers, vol. 38, no. 6, pp. 769-774, June 1989.

Digital Library

[16]

P.D. Hortensius, et al., “Cellular Automata Circuits for Built-In Self Test,” IBM J. Research and Development, vol. 34, March/May 1990.

Digital Library

[17]

P.D. Hortensius R.D. McLeod and H.C. Card, “Cellular Automata Based Signature Analysis for Built-In Self-Test,” IEEE Trans. Computers, vol. 39, no. 10, pp. 1273-1283, Oct. 1990.

Digital Library

[18]

O. Martin A.M. Odlyzko and S. Wolfram, “Algebraic Properties of Cellular Automata,” Comm. Math. Physics, vol. 93, pp. 219-258, 1984.

[19]

M. Serra T. Slater J.C. Muzio and D.M. Miller, “Analysis of One Dimensional Cellular Automata and Their Aliasing Probabilities,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 767-778, July 1990.

Digital Library

[20]

S. Nandi B. Vamsi S. Chakraborty S. Roy and P.P. Chaudhuri, “Delay Fault Test Generation with Cellular Automata,” Proc. Sixth Int'l Conf. VLSI Design, pp. 281-286, Jan. 1993.

[21]

D.R. Chowdhury S. Basu I.S. Gupta and P.P. Chaudhuri, “Design of CAECC—Cellular Automata Based Error Correcting Code,” IEEE Trans. Computers, vol. 43, no. 6, pp. 759-764, June 1994.

Digital Library

[22]

K. Sasidhar S. Chattopadhyay and P.P. Chaudhuri, “CAA Decoder for Cellular Automata Based Byte Error Correcting Code,” IEEE Trans. Computers, vol. 45, no. 9, pp. 1003-1016, Sept. 1996.

Digital Library

[23]

S. Nandi B. K. Kar and P.P. Chaudhuri, “Theory and Application of Cellular Automata in Cryptography,” IEEE Trans. Computers, vol. 43, no. 12, Dec. 1994.

Digital Library

[24]

D. Chowdhury S. Chakraborty B. Vamsi and P. Chaudhuri, “CellularAutomata Based Synthesis of Easily and Fully Testable FSMs,” Proc. Int'l Conf. Computer-Aided Design '93, pp. 650-653, Nov. 1993.

Digital Library

Cited By

Voyiatzis IGizopoulos DPaschalis A(2010)Recursive pseudo-exhaustive two-pattern generationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203130018:1(142-152)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2031300
Tan SGuan S(2009)Randomness quality of permuted pseudorandom binary sequencesMathematics and Computers in Simulation10.1016/j.matcom.2008.07.01279:5(1618-1626)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1016/j.matcom.2008.07.012
Wu SJandhyala SMalaiya YJayasumana A(2008)Antirandom testingVLSI Design10.1155/2008/1657092008:2(1-9)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1155/2008/165709

Index Terms

Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator
1. Hardware

Recommendations

Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
The MIT Press scientific computation series

This paper presents a design technique for linear feedback shift registers that generate test patterns for pseudoexhaustive testing. This technique is applicable to any combinational network in which none of the outputs depends on all inputs. It does ...
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms

Testing for delay and CMOS stuck-open faults requires two-pattern tests, and typically a large number of two pattern tests are needed. Built-in self-test (BIST) schemes are attractive for comprehensive testing of such faults. BIST test pattern ...
Bounds on pseudoexhaustive test lengths

Pseudoexhaustive testing involves applying all possible input patterns to the individual output cones of a combinational circuit. Based on our new algebraic results, we have derived both generic (cone-independent) and circuit-specific (conedependent) ...

Comments

Information & Contributors

Information

Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 50, Issue 2

February 2001

95 pages

ISSN:0018-9340

Editor:
Jean-Luc Gaudiot
Univ. of Southern California, Los Angeles

Issue’s Table of Contents

Copyright © Copyright © 2001 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 February 2001

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

3
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Voyiatzis IGizopoulos DPaschalis A(2010)Recursive pseudo-exhaustive two-pattern generationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203130018:1(142-152)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2031300
Tan SGuan S(2009)Randomness quality of permuted pseudorandom binary sequencesMathematics and Computers in Simulation10.1016/j.matcom.2008.07.01279:5(1618-1626)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1016/j.matcom.2008.07.012
Wu SJandhyala SMalaiya YJayasumana A(2008)Antirandom testingVLSI Design10.1155/2008/1657092008:2(1-9)Online publication date: 1-Jan-2008
https://dl.acm.org/doi/10.1155/2008/165709

View Options

View options

Media

Figures

Other

Tables

View Issue’s Table of Contents