research-article

Algorithm-Based Fault Detection for Signal Processing Applications

Authors:

A. L. N. Reddy,

P. BanerjeeAuthors Info & Claims

IEEE Transactions on Computers, Volume 39, Issue 10

Pages 1304 - 1308

https://doi.org/10.1109/12.59860

Published: 01 October 1990 Publication History

Abstract

The increasing demands for high-performance signal processing along with the availability of inexpensive high-performance processors have results in numerous proposals for special-purpose array processors for signal processing applications. A functional-level concurrent error-detection scheme is presented for such VLSI signal processing architectures as those proposed for the FFT and QR factorization. Some basic properties involved in such computations are used to check the correctness of the computed output values. This fault-detection scheme is shown to be applicable to a class of problems rather than a particular problem, unlike the earlier algorithm-based error-detection techniques. The effects of roundoff/truncation errors due to finite-precision arithmetic are evaluated. It is shown that the error coverage is high with large word sizes.

References

[1]

{1} J. M. Speiser and H. J. Whitehouse, "Parallel processing algorithms and architectures for real-time signal processing," in Proc. SPIE Conf. Real Time Signal Processing IV, vol. 298, 1981.

[2]

{2} K. H. Huang and J. A. Abraham, "Algorithm-based fault tolerance for matrix operations," IEEE Trans. Comput., vol. C-33, pp. 518-528, June 1984.

[3]

{3} P. Banerjee and J. A. Abraham, "Fault-secure algorithms for multiple processor systems," in Proc. 11th Int. Symp. Comput. Architecture, June 1984, pp. 279-287.

[4]

{4} F. T. Luk, "Algorithm-based fault tolerance for parallel matrix solvers," in Proc. SPIE, 1982.

[5]

{5} C. Y. Chen and J. A. Abraham, "Fault-tolerant systems for the computation of eigenvalues and singular values," in Proc. SPIE Conf., Aug. 1986, pp. 228-237.

[6]

{6} J. Y. Jou and J. A. Abraham, "Fault-tolerant FFT networks," IEEE Trans. Comput., vol. C-37, no. 5, pp. 548-561, May 1988.

[7]

{7} R. A. Gabel and R. A. Roberts, Signals and Linear Systems. New York: Wiley, 1980.

[8]

{8} Y.-H. Choi and M. Malek, "A fault-tolerant FFT processor," IEEE Trans. Comput., vol. C-37, no. 5, pp. 617-621, May 1988.

[9]

{9} A. L. Narasimha Reddy, "Algorithm based fault detection techniques for snecific applications," CSG Tech. Rep., Coordinated Sci. Lab., Univ. of Illinois Urbana-Champaign, 1987.

[10]

{10} W. K. Pratt, Digital Image Processing. New York: Wiley, 1978.

[11]

{11} R. N. Bracewell, "The discrete Hartey transform," J. Opt. Soc. Amer., vol. 73, pp. 1832-1835, Dec. 1983.

[12]

{12} W. M. Gentleman and H. T. Kung, "Matrix triangularization by systolic arrays, " in Proc. SPIE, vol. 298, Real Time Signal Processing IV, 1981, pp. 19-26.

[13]

{13} R. J. Gal Ezer, "The wavefront array processor and its applications," Ph.D. dissertation, USC, Los Angeles, Dec. 1982.

[14]

{14} C. J. Weinstein, "Roundoff noise in floating point fast Fourier transform computation," IEEE Trans. Audio Electroacoust., vol. AU-17, pp. 209-215, Sept. 1969.

[15]

{15} J. H. Wilkinson, The Algebraic Eigenvalue Problem. London, England: Oxford University Press, 1965.

Cited By

Savalam CAlapati V(2022)Digital twin based FPGA implementation of FIR filter for multi-bit soft computing error detection and correction for industrial applicationsSoft Computing - A Fusion of Foundations, Methodologies and Applications10.1007/s00500-022-07371-727:7(4289-4306)Online publication date: 29-Aug-2022
https://dl.acm.org/doi/10.1007/s00500-022-07371-7
Gao ZZhang LYan TGuo KXu ZReviriego P(2020)Design of SEU-Tolerant Turbo Decoders Implemented on SRAM-FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.301697628:12(2563-2572)Online publication date: 25-Nov-2020
https://dl.acm.org/doi/10.1109/TVLSI.2020.3016976
Gao ZZhu JHan RXu ZUllah AReviriego P(2019)Design and Implementation of Configuration Memory SEU-Tolerant Viterbi Decoders in SRAM-Based FPGAsIEEE Transactions on Nanotechnology10.1109/TNANO.2019.292587218(691-699)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1109/TNANO.2019.2925872
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Index Terms

Algorithm-Based Fault Detection for Signal Processing Applications
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems
2. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
      1. Scheduling algorithms
    2. Online algorithms
      1. Online learning algorithms
        Scheduling algorithms
  2. Theory and algorithms for application domains
    1. Machine learning theory
      1. Reinforcement learning
        Sequential decision making

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 39, Issue 10

October 1990

99 pages

ISSN:0018-9340

Editor:
Ming T. (Mike) Liu
The Ohio State Univ., Columbus, OH

Issue’s Table of Contents

Copyright © Copyright © 1990 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 October 1990

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Cited By

Savalam CAlapati V(2022)Digital twin based FPGA implementation of FIR filter for multi-bit soft computing error detection and correction for industrial applicationsSoft Computing - A Fusion of Foundations, Methodologies and Applications10.1007/s00500-022-07371-727:7(4289-4306)Online publication date: 29-Aug-2022
https://dl.acm.org/doi/10.1007/s00500-022-07371-7
Gao ZZhang LYan TGuo KXu ZReviriego P(2020)Design of SEU-Tolerant Turbo Decoders Implemented on SRAM-FPGAsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.301697628:12(2563-2572)Online publication date: 25-Nov-2020
https://dl.acm.org/doi/10.1109/TVLSI.2020.3016976
Gao ZZhu JHan RXu ZUllah AReviriego P(2019)Design and Implementation of Configuration Memory SEU-Tolerant Viterbi Decoders in SRAM-Based FPGAsIEEE Transactions on Nanotechnology10.1109/TNANO.2019.292587218(691-699)Online publication date: 1-Jan-2019
https://dl.acm.org/doi/10.1109/TNANO.2019.2925872
Li TAmbrose JRagel RParameswaran S(2016)Processor Design for Soft ErrorsACM Computing Surveys10.1145/299635749:3(1-44)Online publication date: 8-Nov-2016
https://dl.acm.org/doi/10.1145/2996357
Gao ZReviriego PXu ZSu XZhao MWang JMaestro J(2016)Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval ChecksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.240862124:2(769-773)Online publication date: 1-Feb-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2408621
Reviriego PPontarelli SMaestro JOttavi M(2015)A Synergetic Use of Bloom Filters for Error Detection and CorrectionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.231123423:3(584-587)Online publication date: 20-Feb-2015
https://dl.acm.org/doi/10.1109/TVLSI.2014.2311234
Zhen Gao Reviriego PWen Pan Zhan Xu Ming Zhao Jing Wang Maestro J(2015)Fault Tolerant Parallel Filters Based on Error Correction CodesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.230832223:2(384-387)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1109/TVLSI.2014.2308322
Mozaffari-Kermani MManoharan NAzarderakhsh R(2015)Reliable Radix-4 Complex Division for Fault-Sensitive ApplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.239438934:4(656-667)Online publication date: 17-Mar-2015
https://dl.acm.org/doi/10.1109/TCAD.2015.2394389
Reviriego PMaestro JLiu S(2010)Efficient soft error-tolerant adaptive equalizersIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2009.203925257:8(2032-2040)Online publication date: 1-Aug-2010
https://dl.acm.org/doi/10.1109/TCSI.2009.2039252
Ashouei MChatterjee A(2009)Checksum-based probabilistic transient-error compensation for linear digital systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200458717:10(1447-1460)Online publication date: 1-Oct-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2004587
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