research-article

Comprehensive Testing of Multistage Interconnection Networks

Authors:

Antoine Mourad,

Miroslaw MalekAuthors Info & Claims

IEEE Transactions on Computers, Volume 40, Issue 8

Pages 935 - 951

https://doi.org/10.1109/12.83638

Published: 01 August 1991 Publication History

Abstract

The authors present efficient methods for testing packet-switched multistage interconnection networks. In addition to testing the data paths and routing capabilities, tests for detecting faults in the control circuitry including the conflict resolution capabilities are provided. Using a general model of the switch, testing sequences are constructed for the internal functions of the f*f switch requiring only O(f/sup 2/2/sup f/) tests in the case of round-robin priority and O(f2/sup f-1/) in the case of fixed priority (f is usually a constant that is less than or equal to eight). Algorithms are then presented to test the entire network using at most twice the number of tests needed to test a switch, independently of the network size, which results in O(log N) testing time for an N-processor network. It is shown that the method achieves higher coverage and several-orders-of-magnitude reduction in the testing time of complex multiprocessor systems compared to previous methods.

References

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Digital Library

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{8} W. Y.-P. Lim, "A test strategy for packet switching networks," in Proc. Int. Conf. Parallel Processing, Aug. 1982, pp. 96-98.

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Digital Library

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Digital Library

Cited By

Liu BLombardi FPark NChoi M(2004)Testing Layered Interconnection NetworksIEEE Transactions on Computers10.1109/TC.2004.1753:6(710-722)Online publication date: 1-Jun-2004
https://dl.acm.org/doi/10.1109/TC.2004.17
Bataineh SAllosl B(2001)Fault-Tolerant Multistage Interconnection NetworkTelecommunications Systems10.5555/2727160.272766317:4(455-472)Online publication date: 1-Aug-2001
https://dl.acm.org/doi/10.5555/2727160.2727663
Wang S(2001)Distributed Diagnosis in Multistage Interconnection NetworksJournal of Parallel and Distributed Computing10.1006/jpdc.2000.167561:2(254-264)Online publication date: 1-Feb-2001
https://dl.acm.org/doi/10.1006/jpdc.2000.1675
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Comprehensive Testing of Multistage Interconnection Networks

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 40, Issue 8

August 1991

96 pages

ISSN:0018-9340

Editor:
Earl Swartzlander
Univ. of Texas, Austin

Issue’s Table of Contents

Copyright © Copyright © 1991 IEEE. All Rights Reserved.

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IEEE Computer Society

United States

Publication History

Published: 01 August 1991

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Cited By

Liu BLombardi FPark NChoi M(2004)Testing Layered Interconnection NetworksIEEE Transactions on Computers10.1109/TC.2004.1753:6(710-722)Online publication date: 1-Jun-2004
https://dl.acm.org/doi/10.1109/TC.2004.17
Bataineh SAllosl B(2001)Fault-Tolerant Multistage Interconnection NetworkTelecommunications Systems10.5555/2727160.272766317:4(455-472)Online publication date: 1-Aug-2001
https://dl.acm.org/doi/10.5555/2727160.2727663
Wang S(2001)Distributed Diagnosis in Multistage Interconnection NetworksJournal of Parallel and Distributed Computing10.1006/jpdc.2000.167561:2(254-264)Online publication date: 1-Feb-2001
https://dl.acm.org/doi/10.1006/jpdc.2000.1675
Bhatia MYoussef A(1998)Performance analysis and fault tolerance of randomized routing on Clos networksTelecommunications Systems10.1023/A:101911501638810:1-2(157-173)Online publication date: 1-Oct-1998
https://dl.acm.org/doi/10.1023/A%3A1019115016388
Qiao C(1997)A Two-Level Process for Diagnosing Crosstalk in Photonic Dilated Benes NetworksJournal of Parallel and Distributed Computing10.1006/jpdc.1996.128441:1(53-66)Online publication date: 25-Feb-1997
https://dl.acm.org/doi/10.1006/jpdc.1996.1284
Bernard ESimon SNossek J(1996)Built-in self test architectures for multistage interconnection networksProceedings of the 1996 European conference on Design and Test10.5555/787259.787621Online publication date: 11-Mar-1996
https://dl.acm.org/doi/10.5555/787259.787621

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