research-article

Testing Layered Interconnection Networks

Authors:

Fabrizio Lombardi,

Minsu ChoiAuthors Info & Claims

IEEE Transactions on Computers, Volume 53, Issue 6

Pages 710 - 722

https://doi.org/10.1109/TC.2004.17

Published: 01 June 2004 Publication History

Abstract

Abstract--This paper presents an approach for fault detection in layered interconnection networks (LINs). An LIN is a generalized multistage interconnection network commonly used in reconfigurable systems; the nets (links) are arranged in sets (referred to as layers) of different size. Switching elements (made of simple switches such as transmission-gate-like devices) are arranged in a cascade to connect pairs of layers. The switching elements of an LIN have the same number of switches, but the switching patterns may not be uniform. A comprehensive fault model for the nets and switches is assumed at physical and behavioral levels. Testing requires configuring the LIN multiple times. Using a graph approach, it is proven that the minimal set of configurations corresponds to the node disjoint path sets. The proposed approach is based on two novel results in the execution of the network flow algorithm to find node disjoint path sets, while retaining optimality in the number of configurations. These objectives are accomplished by finding a feasible flow such that the maximal degree can be iteratively decreased, while guaranteeing the existence of an appropriate circulation. Net adjacencies are also tested for possible bridge faults (shorts). To account for 100 percent fault coverage of bridge faults a postprocessing algorithm may be required; bounds on its complexity are provided. The execution complexity of the proposed approach (inclusive of test vector generation and post-processing) is O(N^4 WL), where N is the total number of nets, W is the number of switches per switching element, and L is the number of layers. Extensive simulation results are provided.

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Cited By

Ruan AHuang HWang JZhao Y(2016)A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAsJournal of Electronic Testing: Theory and Applications10.1007/s10836-016-5622-032:6(749-762)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10836-016-5622-0

Index Terms

Testing Layered Interconnection Networks
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
  2. Dependable and fault-tolerant systems and networks
2. General and reference
  1. Cross-computing tools and techniques
    1. Reliability

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 53, Issue 6

June 2004

144 pages

ISSN:0018-9340

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Copyright © Copyright © 2004 IEEE. All Rights Reserved.

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IEEE Computer Society

United States

Publication History

Published: 01 June 2004

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Cited By

Ruan AHuang HWang JZhao Y(2016)A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAsJournal of Electronic Testing: Theory and Applications10.1007/s10836-016-5622-032:6(749-762)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10836-016-5622-0

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