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A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems

Authors:

Mohammed A. S. Khalid,

Jonathan RoseAuthors Info & Claims

FPGA '98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

Pages 45 - 54

https://doi.org/10.1145/275107.275119

Published: 01 March 1998 Publication History

Abstract

Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture; the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed [Arno92] [Butt92] [Hauc94] [Apti96] [Vuil96] and previous research has shown that the partial crossbar is one of the best existing architectures [Kim96] [Khal97]. In this paper we propose a new routing architecture, called the Hybrid Complete-Graph and Partial-Crossbar (HCGP) which has superior speed and cost compared to a partial crossbar. The new architecture uses both hard-wired and programmable connections between the FPGAs.

We compare the performance and cost of the HCGP and partial crossbar architectures experimentally, by mapping a set of 15 large benchmark circuits into each architecture. A customized set of partitioning and inter-chip routing tools were developed, with particular attention paid to architecture-appropriate inter-chip routing algorithms. We show that the cost of the partial crossbar (as measured by the number of pins on all FPGAs and FPIDs required to fit a design), is on average 20% more than the new HCGP architecture and as much as 35% more. Furthermore, the critical path delay for designs implemented on the partial crossbar increased, and were on average 9% more than the HCGP architecture and up to 26% more.

Using our experimental approach, we also explore a key architecture parameter associated with the HCGP architecture: the proportion of hard-wired connections versus programmable connections, to determine its best value.

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Index Terms

A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
1. Hardware
2. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
      1. Routing and network design problems

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cover image ACM Conferences

FPGA '98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

March 1998

262 pages

ISBN:0897919785

DOI:10.1145/275107

Chairmen:
Jason Cong
Univ. of California, Los Angeles
,
Sinan Kaptanoglu
Actel Corp.

Copyright © 1998 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 March 1998

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FPGA98: 1998 International Symposium on Field Programmable Gate Arrays

February 22 - 25, 1998

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Meng HZhao QYoshida T(2022)A Study of Reconfigurable Switch Architecture for Chiplets Interconnection2022 Tenth International Symposium on Computing and Networking Workshops (CANDARW)10.1109/CANDARW57323.2022.00049(69-75)Online publication date: Nov-2022
https://doi.org/10.1109/CANDARW57323.2022.00049
Zhao Dan Xu Guodong Geng Yunhai (2008)Problems of Micro-satellite OBC and solving method based on reconfiguration technique2008 2nd International Symposium on Systems and Control in Aerospace and Astronautics10.1109/ISSCAA.2008.4776233(1-4)Online publication date: Dec-2008
https://doi.org/10.1109/ISSCAA.2008.4776233
Dickin DShannon L(2008)Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platformsProceedings of the 2008 International Conference on Application-Specific Systems, Architectures and Processors10.1109/ASAP.2008.4580156(67-72)Online publication date: 2-Jul-2008
https://dl.acm.org/doi/10.1109/ASAP.2008.4580156
Macias NAthanas P(2007)Application of Self-Configurability for Autonomous, Highly-Localized Self-RegulationProceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems10.1109/AHS.2007.32(397-404)Online publication date: 5-Aug-2007
https://dl.acm.org/doi/10.1109/AHS.2007.32
Khalid MRose J(2006)Hardwired-clusters partial-crossbar: A hierarchical routing architecture for multi-FPGA systemsParallel and Distributed Processing10.1007/BFb0097944(597-605)Online publication date: 28-Oct-2006
https://doi.org/10.1007/BFb0097944
Srinivasan VRadhakrishnan SVemuri RWalrath J(2006)Interconnect synthesis for reconfigurable multi-FPGA architecturesParallel and Distributed Processing10.1007/BFb0097943(588-596)Online publication date: 28-Oct-2006
https://doi.org/10.1007/BFb0097943
Banovic KKhalid MAbdel-Raheem E(2005)FPGA-based rapid prototyping of digital signal processing systems48th Midwest Symposium on Circuits and Systems, 2005.10.1109/MWSCAS.2005.1594184(647-650 Vol. 1)Online publication date: 2005
https://doi.org/10.1109/MWSCAS.2005.1594184
Liu BLombardi FPark NChoi M(2004)Testing Layered Interconnection NetworksIEEE Transactions on Computers10.1109/TC.2004.1753:6(710-722)Online publication date: 1-Jun-2004
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Kuusilinna KChang CAmmer MRichards BBrodersen R(2003)Designing BEEEURASIP Journal on Advances in Signal Processing10.1155/S11108657032121542003(502-513)Online publication date: 1-Jan-2003
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Chang CKuusilinna KRichards BBrodersen RTrimberger STessier R(2003)Implementation of BEEProceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays10.1145/611817.611832(91-99)Online publication date: 23-Feb-2003
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