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Board-level multiterminal net routing for FPGA-based logic emulation

Authors:

Wai-Kei Mak,

D. F. WongAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 2, Issue 2

Pages 151 - 167

https://doi.org/10.1145/253052.253136

Published: 01 April 1997 Publication History

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Abstract

We consider a board-level routing problem applicable to FPGA-based logic emulation systems such as the Realizer System [Varghese et al. 1993] and the Enterprise Emulation System [Maliniak 1992] manufactured by Quickturn Design Systems. Optimal algorithms have been proposed for the case where all nets are two-terminal nets [Chan and Schlag 1993; Mak and Wong 1995]. We show how multiterminal nets can be handled by decomposition into two-terminal nets. We show that the multiterminal net decomposition problem can be modeled as a bounded-degree hypergraph-to-graph transformation problem where hyperedges are transformed to spanning trees. A network flow-based algorithm that solves both problems is proposed. It determines if there is a feasible decomposition and gives one whenever such a decomposition exists.

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Cited By

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Tara NHasan Babu HJamal L(2017)Power efficient optimum design of the Reversible Plessey Logic Block of a field-programmable gate arraySustainable Computing: Informatics and Systems10.1016/j.suscom.2017.09.00416(76-92)Online publication date: Dec-2017
https://doi.org/10.1016/j.suscom.2017.09.004
Turki MMarrakchi ZMehrez HAbid M(2013)Frequency optimization objective during system prototyping on multi-FPGA platformInternational Journal of Reconfigurable Computing10.1155/2013/8535102013(9-9)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1155/2013/853510
Tang QMehrez HTuna M(2013)Routing algorithm for multi-FPGA based systems using multi-point physical tracks2013 International Symposium on Rapid System Prototyping (RSP)10.1109/RSP.2013.6683951(2-8)Online publication date: Oct-2013
https://doi.org/10.1109/RSP.2013.6683951
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Board-level multiterminal net routing for FPGA-based logic emulation
1. Hardware

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Reviews

Reviewer: Andrew Donald Booth

Field-programmable gate arrays (FPGAs) can be used effectively to emulate complex digital systems. This paper is concerned with their use in the emulation of complex digital designs. In a previous paper [1], the authors showed that the board-level routing problem is NP-complete, and they now show how a relaxation of constraints can make the problem solvable. A network flow–based algorithm is given in pseudo c ode form, and three lemmas establish its viability. The paper ends with a table that shows the result of practical experiments with the method.

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 2, Issue 2

April 1997

112 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/253052

Issue’s Table of Contents

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 April 1997

Published in TODAES Volume 2, Issue 2

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Cited By

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Tara NHasan Babu HJamal L(2017)Power efficient optimum design of the Reversible Plessey Logic Block of a field-programmable gate arraySustainable Computing: Informatics and Systems10.1016/j.suscom.2017.09.00416(76-92)Online publication date: Dec-2017
https://doi.org/10.1016/j.suscom.2017.09.004
Turki MMarrakchi ZMehrez HAbid M(2013)Frequency optimization objective during system prototyping on multi-FPGA platformInternational Journal of Reconfigurable Computing10.1155/2013/8535102013(9-9)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1155/2013/853510
Tang QMehrez HTuna M(2013)Routing algorithm for multi-FPGA based systems using multi-point physical tracks2013 International Symposium on Rapid System Prototyping (RSP)10.1109/RSP.2013.6683951(2-8)Online publication date: Oct-2013
https://doi.org/10.1109/RSP.2013.6683951
Shamsujjoha MHasan Babu HJamal L(2013)Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesisMicroelectronics Journal10.1016/j.mejo.2013.02.00544:6(519-537)Online publication date: Jun-2013
https://doi.org/10.1016/j.mejo.2013.02.005
Turki MMarrakchi ZMehrez HAbid M(2013)Iterative routing algorithm of Inter-FPGA signals for Multi-FPGA prototyping platformProceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications10.1007/978-3-642-36812-7_20(210-217)Online publication date: 25-Mar-2013
https://dl.acm.org/doi/10.1007/978-3-642-36812-7_20
Ejnioui ARanganathan N(2003)Multiterminal net routing for partial crossbar-based multi-FPGA systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.80052311:1(71-78)Online publication date: 1-Feb-2003
https://dl.acm.org/doi/10.1109/TVLSI.2002.800523
Compton KHauck S(2002)Reconfigurable computingACM Computing Surveys10.1145/508352.50835334:2(171-210)Online publication date: 1-Jun-2002
https://dl.acm.org/doi/10.1145/508352.508353
Chen HWong DMak WYang HRoy KKang SKoh C(2001)Faster and more accurate wiring evaluation in interconnect-centric floorplanningProceedings of the 11th Great Lakes symposium on VLSI10.1145/368122.368798(62-67)Online publication date: 1-Mar-2001
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Khalid MRose J(2000)A novel and efficient routing architecture for multi-FPGA systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.8207598:1(30-39)Online publication date: 1-Feb-2000
https://dl.acm.org/doi/10.1109/92.820759
Ejnioui ARanganathan NKaptanoglu STrimberger S(1999)Multi-terminal net routing for partial crossbar-based multi-FPGA systemsProceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays10.1145/296399.296454(176-185)Online publication date: 1-Feb-1999
https://dl.acm.org/doi/10.1145/296399.296454
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