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A novel predictable segmented FPGA routing architecture
- Emil S. Ochotta,
- Patrick J. Crotty,
- Charles R. Erickson,
- Chih-Tsung Huang,
- Rajeev Jayaraman,
- Richard C. Li,
- Joseph D. Linoff,
- Luan Ngo,
- Hy V. Nguyen,
- Kerry M. Pierce,
- Douglas P. Wieland,
- Jennifer Zhuang,
- Scott S. Nance
In the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented [1], novel, segmented routing fabric that is targeted to high performance ...
More wires and fewer LUTs: a design methodology for FPGAs
- Atsushi Takahara,
- Toshiaki Miyazaki,
- Takahiro Murooka,
- Masaru Katayama,
- Kazuhiro Hayashi,
- Akihiro Tsutsui,
- Takaki Ichimori,
- Ken-nosuke Fukami
In designing FPGAs, it is important to achiev e a good balance bet w een the number of logic blocks, suc h has Look-Up Tables (LUTs), and wiring resources. It is difficult to find an optimal solution. In this paper, w e presen t an FPGA design ...
Optimizations for a highly cost-efficient programmable logic architecture
Architects of programmable logic devices (PLDs) face several challenges when optimizing a new device family for low manufacturing cost. When given an aggressive die-size goal, functional blocks that seem otherwise insignificant become targets for area ...
Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation
In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but also can implement some wide functions of more than K variables. We apply ...
A new retiming-based technology mapping algorithm for LUT-based FPGAs
In this paper, w e presen t a new retiming-based technology mapping algorithm for look-up table-based field programmable gate arrays. The algorithm is based on a novel iterative procedure for computing all k-cuts of all nodes in a sequen tialcircuit, in ...
A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture; the manner in which wires, FPGAs and Field-Programmable ...
Managing pipeline-reconfigurable FPGAs
While reconfigurable computing promises to deliver incomparable performance, it is still a marginal technology due to the high cost of developing and upgrading applications. Hardware virtualization can be used to significantly reduce both these costs. ...
Configuration prefetch for single context reconfigurable coprocessors
Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal with this overhead, and increase the power of reconfigurable systems, it is important to develop hardware and ...
Circuit partitioning with complex resource constraints in FPGAs
In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not ...
Timing driven floorplanning on programmable hierarchical targets
The goal of this paper is to perform a timing optimization of a circuit described b y a network of cells on a target structure whose connection delays ha v ediscrete values follo wing its hierarch y. The circuits is modelled by a set of timed cones ...
Bridging fault detection in FPGA interconnects using IDDQ
This paper presents a vector generation approach for testing interconnects in configurable (SRAM-based) Field Programmable Gate Arrays (FPGAs). The proposed approach detects bridging faults and is based on quiescent current (IDDQ monitoring. Compared ...
Efficiently supporting fault-tolerance in FPGAs
While system reliability is conventionally achieved through component replication, we have developed a fault-tolerance approach for FPGA-based systems that comes at a reduced cost in terms of design time, volume, and weight. We partition the physical ...
Constraints from hell; how to tell makes a good FPGA (panel)
The FPGA development is an extraordinarily complex task, involving many people working in architecture, chip design, software, marketing and production. Each tends to focus on their immediate task, and have their own measures of goodness for what they ...
Fast module mapping and placement for datapaths in FPGAs
By tailoring a compiler tree-parsing tool for datapath module mapping, we produce good quality results for datapath synthesis in very fast run time. Rather than flattening the design to gates, we preserve the datapath structure; this allows exploitation ...
Fast integrated tools for circuit design with FPGAs
To implement high-density and high-speed FPGA circuits, designers need tight control over the circuit implementation process. However, current design tools are unsuited for this purpose as they lack fast turnaround times, interactiveness, and ...
A fast routability-driven router for FPGAs
Three factors are driving the demand for rapid FPGA compilation. First, as FPGAs have grown in logic capacity, the compile computation has grown more quickly than the compute power of the available computers. Second, there exists a subset of users who ...
Scheduling designs into a time-multiplexed FPGA
An algorithm is presented for partitioning a design in time. The algorithm devides a large, technology-mapped design into multiple configurations of a time-multiplexed FPGA. These configurations are rapidly executed in the FPGA to emulate the large ...
Partitioning sequential circuits on dynamically reconfiguable FPGAs
A fundamental feature of Dynamically Reconfigurable FP-GAs (DRFPGAs) is that the logic and interconnect is time-multiplexed. Thus for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a ...
SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays
It has become clear that large embedded configurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage parts of circuits. Unfortunately, they require the FPGA vendor to ...
Technology mapping for FPGAs with embedded memory blocks
Modern field programmable gate arrays (FPGAs) provide embedded memory blocks (EMBs) to be used as on-chip memories. In this paper, we explore the possibility of using EMBs to implement logic functions when they are not used as on-chip memory. We propose ...
A survey of CORDIC algorithms for FPGA based computers
The current trend back toward hardware intensive signal processing has uncovered a relative lack of understanding of hardware signal processing architectures. Many hardware efficient algorithms exist, but these are generally not well known due to the ...
FPGA-based sonar processing
This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays. Additionally, we show that our proposed ...
Evolving computer programs using rapidly reconfigurable field-programmable gate arrays and genetic programming
This paper describes how the massive parallelism of the rapidly reconfigurable Xilinx XC6216 FPGA (in conjunction with Virtual Computing's H.O.T. Works board) can be exploited to accelerate the time-consuming fitness measurement task of genetic ...
High-performance carry chains for FPGAs
Carry chains are an important consideration for most computations, including FPGAs. Current FPGAs dedicate a portion of their logic to support these demands via a simple ripple carry scheme. In this paper we demonstrate how more advanced carry ...
A coarse-grained FPGA architecture for high-performance FIR filtering
This paper introduces a coarse-grained FPGA architecture that is specialized for high-performance Finite Impulse Response (FIR) filtering. The proposed architecture provides the flexibility of a DSP processor with performance and area efficiency similar ...
An LPGA with foldable PLA-style logic blocks
Laser-programmed gate arrays (LPGAs) represent a new approach to application specific integrated circuit prototyping and implementation. This paper proposes a new LPGA logic block architecture called a foldable PLA-style logic block. The proposed logic ...
Index Terms
- Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays