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Circuit partitioning with complex resource constraints in FPGAs

Authors:

D. F. WongAuthors Info & Claims

FPGA '98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

March 1998

Pages 77 - 84

https://doi.org/10.1145/275107.275122

Published: 01 March 1998 Publication History

Abstract

In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing capacity and diverse resource types in the new FPGA architectures. We propose a network flow based method to optimally check whether a circuit or a sub-circuit is feasible for a set of available heterogeneous resources. The feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementations. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple FPGA designs (e.g. logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical FPGA (e.g. Actel's ES6500 FPGA family).

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Cited By

Gregerson AChadha AMorrow K(2013)Multi-personality partitioning for heterogeneous systems2013 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2013.6718375(314-317)Online publication date: Dec-2013
https://doi.org/10.1109/FPT.2013.6718375
Selvakkumaran NRanjan ARaje SKarypis GMalik SFix LKahng A(2004)Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resourcesProceedings of the 41st annual Design Automation Conference10.1145/996566.996768(741-746)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996768
Bao XAreibi S(2004)Constructive and local search heuristic techniques for FPGA placementCanadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513)10.1109/CCECE.2004.1345073(505-508)Online publication date: 2004
https://doi.org/10.1109/CCECE.2004.1345073
Show More Cited By

Index Terms

Circuit partitioning with complex resource constraints in FPGAs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Very large scale integration design
    1. Application-specific VLSI designs
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems

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Published In

cover image ACM Conferences

FPGA '98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays

March 1998

262 pages

ISBN:0897919785

DOI:10.1145/275107

Chairmen:
Jason Cong
Univ. of California, Los Angeles
,
Sinan Kaptanoglu
Actel Corp.

Copyright © 1998 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 March 1998

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FPGA98

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SIGDA

FPGA98: 1998 International Symposium on Field Programmable Gate Arrays

February 22 - 25, 1998

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Gregerson AChadha AMorrow K(2013)Multi-personality partitioning for heterogeneous systems2013 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2013.6718375(314-317)Online publication date: Dec-2013
https://doi.org/10.1109/FPT.2013.6718375
Selvakkumaran NRanjan ARaje SKarypis GMalik SFix LKahng A(2004)Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resourcesProceedings of the 41st annual Design Automation Conference10.1145/996566.996768(741-746)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996768
Bao XAreibi S(2004)Constructive and local search heuristic techniques for FPGA placementCanadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513)10.1109/CCECE.2004.1345073(505-508)Online publication date: 2004
https://doi.org/10.1109/CCECE.2004.1345073
Wolz FKolla R(2001)Bubble Partitioning for LUT-Based Sequential CircuitsField-Programmable Logic and Applications10.1007/3-540-44687-7_35(336-345)Online publication date: 17-Aug-2001
https://doi.org/10.1007/3-540-44687-7_35
Lee HWang TYoshida K(2000)Feasible two-way circuit partitioning with complex resource constraintsProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368731(435-440)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368731
Hsun-Cheng Lee Ting-Chi Wang (2000)Feasible two-way circuit partitioning with complex resource constraintsProceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)10.1109/ASPDAC.2000.835139(435-440)Online publication date: 2000
https://doi.org/10.1109/ASPDAC.2000.835139

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