A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem
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P. BoseAuthors Info & Claims
P. BoseAuthors Info & ClaimsAbstract
A technique is presented for formulating the logic/fault simulation of VLSI array logic in terms of standard vector and matrix operation primitives that are well supported on all scientific supercomputers, high-end mainframes, and minisupercomputers that provide vector parallel hardware and software. The overall computing environment is assumed to be a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically intensive applications.
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- A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem
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Copyright © Copyright © 1988 IEEE. All Rights Reserved.
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Published: 01 December 1988
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