research-article

Cray X-MP: The Birth of a Supercomputer

Authors:

Melvin C. August,

Gerald M. Brost,

Christopher C. Hsiung,

Alan J. SchifflegerAuthors Info & Claims

Computer, Volume 22, Issue 1

Pages 45 - 52

https://doi.org/10.1109/2.19822

Published: 01 January 1989 Publication History

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Abstract

The authors' experience in designing and manufacturing the Cray X-MP supercomputer is described. The X-MP is a multiprocessor design built on the basic architecture of the Cray-1 and incorporates the 16-gate emitter-coupled logic gate arrays used in the Cray-2 project. The goal was a two-processor machine compatible with the Cray-1 but with performance 1.5 to 2 times better. The authors examine the architectural considerations. They discuss the use of electronic design rules and CAD (computer-aided design); the packaging, interconnections, and cooling; and assembly and testing

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Reviews

Reviewer: Peter C. Patton

This paper credits Les Davis with the conception of the Cray X-MP multiprocessor as an extension of the architecture of the original Cray-1 supercomputer. It focuses on the design trade-off issues that arose during the engineering team's effort to create a multiprocessor based on an extended Cray-1 instruction set architecture but composed of the 16-gate ECL gate arrays that had been selected for the Cray-2 project. The X-MP design addressed and solved the following problems with the Cray-1: (1)The one-port memory design of the Cray-1 can become a serious performance bottleneck for some FORTRAN programs. (2)The Cray-1 fixed chain-slot-time scheme can be inconvenient for programmers and compilers. (3)The Cray-1 lacks a gather/scatter feature, which would allow vectorization of table lockup codes, sparse matrix computations, and conditional loops. (4)The Cray-1 blocks all other instructions from issuing during an address-cache or data-cache register block-transfer. The developers see this as the main scalar performance bottleneck in the Cray-1. (5)The presence of two sets of scalar registers in the Cray-1 with different word lengths creates complexity in register allocation, scheduling, and data movement between address and scalar (data) registers. (6)The lack of a vector masked store requires storing back unmodified data on the Cray-1. (7)The lack of bit-reverse operations on the Cray-1 makes “bit-fiddling” codes (used in FFT calculation, image and signal processing, and weather and seismic modeling) perform poorly. The design of a single-processor CPU was the first step. The second was a shared memory that can support up to four memory ports, two vector loads, a vector store, and an I/O port for each of four processors and has the additional ability to support chaining at any point in the vector data stream. The designers met the bandwidth requirement of this memory by interleaving 64 banks of real memory. The paper goes on to describe the design process, the solution of the Cray-1 compatibility problem, interprocessor communication, the ECAD design rules, packaging, interconnection, and cooling. While the Cray X-MP was not the first multiprocessor, it was the first multiprocessor supercomputer. As such, it started a design trend in 1980 that will culminate by 1990 in multiprocessor designs from all supercomputer manufacturers. While Steve Chen is (used to be__ __) widely profiled by Cray Research as the father of the X-MP architecture, this paper does not mention his contributions.

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Published In

Computer Volume 22, Issue 1

January 1989

87 pages

ISSN:0018-9162

Editor:
Bruce Shriver
Univ. of Hawaii

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 January 1989

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Gonzalez AKolli AKhan SLiu SDadu VKarandikar SChang JAsanovic KRanganathan PSolihin YHeinrich M(2023)Profiling Hyperscale Big Data ProcessingProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589082(1-16)Online publication date: 17-Jun-2023
Dolbeau R(2018)Theoretical peak FLOPS per instruction set: a tutorialThe Journal of Supercomputing10.1007/s11227-017-2177-574:3(1341-1377)Online publication date: 1-Mar-2018
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Graham RBureddy DLui PRosenstock HShainer GBloch GGoldenerg DDubman MKotchubievsky SKoushnir VLevi LMargolin ARonen TShpiner AWertheim OZahavi E(2016)Scalable hierarchical aggregation protocol (SHArP)Proceedings of the First Workshop on Optimization of Communication in HPC10.5555/3018058.3018059(1-10)Online publication date: 13-Nov-2016
Chang HSung WAltman E(2008)Efficient vectorization of SIMD programs with non-aligned and irregular data access hardwareProceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems10.1145/1450095.1450121(167-176)Online publication date: 19-Oct-2008
Ahn JErez MDally WHorner-Miller B(2006)The design space of data-parallel memory systemsProceedings of the 2006 ACM/IEEE conference on Supercomputing10.1145/1188455.1188540(80-es)Online publication date: 11-Nov-2006
Ciricescu SEssick RLucas BMay PMoat KNorris JSchuette MSaidi A(2003)The Reconfigurable Streaming Vector Processor (RSVPTM)Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture10.5555/956417.956540Online publication date: 3-Dec-2003
Culler DSingh JGupta A(1998)Parallel Computer ArchitectureundefinedOnline publication date: 29-Sep-1998
Kitai KIsobe TSakakibara TYazawa STamaki YTanaka TIshii KGurd JJalby W(1994)Distributed storage control unit for the Hitachi S-3800 multivector supercomputerProceedings of the 8th international conference on Supercomputing10.1145/181181.181183(1-10)Online publication date: 16-Jul-1994
Elzen BMacKenzie D(1994)The Social Limits of SpeedIEEE Annals of the History of Computing10.1109/85.25185416:1(46-61)Online publication date: 1-Mar-1994
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Cited By

Index Terms

Recommendations

A comparison of parallel processing on CRAY X-MP AND IBM 3090 VF multiprocessors

Performance comparison of the Cray-2 and Cray X-MP/416 supercomputers

Vector performance analysis of three supercomputers: Cray 2, Cray Y-MP, and ETA 10-Q

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