research-article

A Case for Intelligent RAM

Authors:

David Patterson,

Thomas Anderson,

Kimberly Keeton,

Christoforos Kozyrakis,

Katherine YelickAuthors Info & Claims

IEEE Micro, Volume 17, Issue 2

Pages 34 - 44

https://doi.org/10.1109/40.592312

Published: 01 March 1997 Publication History

Abstract

Two trends call into question the current practice of microprocessors and DRAMs being fabricated as different chips on different fab lines: 1) the gap between processor and DRAM speed is growing at 50% per year; and 2) the size and organization of memory on a single DRAM chip is becoming awkward to use in a system, yet size is growing at 60% per year. Intelligent RAM, or IRAM, merges processing and memory into a single chip to lower memory latency, increase memory bandwidth, and improve energy efficiency as well as to allow more flexible selection of memory size and organization. In addition, IRAM promises savings in power and board area. We review the state of microprocessors and DRAMs today, explore some of the opportunities and challenges for IRAMs, and finally estimate performance and energy efficiency of three IRAM designs.

References

[1]

J.L. Hennessy and D.A. Patterson, Computer Organization and Design, 2nd ed., Morgan Kaufmann Publishers, San Francisco, 1997.

Digital Library

[2]

Z. Cvetanovic and D. Bhandarkar, "Performance Characterization of the Alpha 21164 Microprocessor Using TP and SPEC Workloads," Proc. Second Int'l Symp. High-Performance Computer Architecture, IEEE Computer Society Press, Los Alamitos, Calif., 1996. pp. 270-280.

Digital Library

[3]

D. Patterson, et al., "Intelligent RAM (IRAM): Chips That Remember and Compute," Dig. Technical Papers, 1997 IEEE Int'l Solid-State Circuits Conf., IEEE, Piscataway, N.J., 1997, pp. 224-225.

[4]

S.A. Przybylski, New DRAM Technologies: A Comprehensive Analysis of the New Architectures, MicroDesign Resources, Sebastopol, California, 1994.

Digital Library

[5]

I.M. Barron, "The Transputer," The Microprocessor and Its Application, D. Aspinall, ed., Cambridge University Press, London, 1978, pp. 343-357.

[6]

P.M. Kogge, et al., "Combined DRAM and Logic Chip for Massively Parallel Systems," Proc. 16th Conf. Advanced Research in VLSI, IEEE CS Press, 1995, pp. 4-16.

Digital Library

[7]

M.D. Noakes D.A. Wallach and W.J. Dally, "The J-Machine Multicomputer: An Architectural Evaluation," Proc. 20th Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 1993, pp. 224-235.

Digital Library

[8]

D. Burger J.R. Goodman and A. Kagi, "Memory Bandwidth Limitations of Future Microprocessors," Proc. 23rd Ann. Int'l Symp. Computer Architecture, IEEE CS Press, 1996, pp. 78-89.

Digital Library

[9]

S.E. Perl and R.L. Sites, "Studies of Windows NT Performance Using Dynamic Execution Traces," Proc. Second Symp. Operating Systems Design and Implementation, 1996, pp. 169-183.

Digital Library

[10]

W.A. Wulf and S.A. McKee, "Hitting the Memory Wall: Implications of the Obvious," Computer Architecture News, Vol. 23, No. 1, Mar. 1995, pp. 20-24.

Digital Library

[11]

R. Fromm, et al., "The Energy Efficiency of IRAM Architectures," submitted to ISCA 97: The 24th Ann. Int'l Symp. Computer Architecture, proceedings to be published by IEEE CS Press, 1997.

Digital Library

[12]

G. Giacalone, et al., "A 1MB, 100MHz Integrated L2 Cache Memory and 128b Interface and ECC Protection," Proc. Int'l Solid-State Circuits Conf., IEEE, 1996, pp. 370-371.

[13]

M.F. Deering S.A. Schlapp and M.G. Lavelle, "FBRAM: A New Form of Memory Optimized for 3D Graphics," Proc. SIGGRAPH 94, Assn. for Computing Machinery, New York, 1994, pp. 167-174.

Digital Library

[14]

T. Shimizu, et al., "A Multimedia 32 b RISC Microprocessor with 16 Mb DRAM," Dig. Technical Papers, 1996 IEEE Int'l Solid-State Circuits Conf., IEEE, 1996 pp. 216-217, 448.

[15]

A. Saulsbury F. Pong and A. Nowatzk, "Missing the Memory Wall: The Case for Processor/Memory Integration," Int'l Symp. Computer Architecture, IEEE CS Press, 1996, pp. 90-101.

Digital Library

[16]

M. Fillo, et al., "The M-Machine Multicomputer," Proc. MICRO 95: 28th Ann. IEEE/ACM Int'l Symp. Microarchitecture, IEEE, 1995, pp. 146-156.

Digital Library

[17]

K. Murakami S. Shirakawa and H. Miyajima, "Parallel Processing RAM Chip with 256Mb DRAM and Quad Processor," Dig. Technical Papers, 1997 IEEE Int'l Solid-State Circuits Conf., IEEE, 1997, pp. 228-229.

[18]

Y. Aimoto, et al., "A 7.68 GIPS 3,84 GB/s 1W Parallel Image Processing RAM Integrating a 16 Mb DRAM and 128 Processors," Dig. Technical Papers, 1996 IEEE Int'l Solid-State Circuits Conf., IEEE, 1996, pp. 372-373, 476.

[19]

D.G. Elliott W.M. Snelgrove and M. Stumm, "Computational RAM: A Memory-SIMD Hybrid and Its Application to DSP," Proc. Custom Integrated Circuits Conf., IEEE, 1992, pp. 30.6.1-30.6.4.

Cited By

Li CZhou ZWang YYang FCao TYang MLiang YSun GTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)PIM-DL: Expanding the Applicability of Commodity DRAM-PIMs for Deep Learning via Algorithm-System Co-OptimizationProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640376(879-896)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620665.3640376
Li XGao MRen ZYu KLu WDai CHu WPeng CWu X(2024)A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MACMicroelectronics Journal10.1016/j.mejo.2024.106124145:COnline publication date: 1-Mar-2024
https://dl.acm.org/doi/10.1016/j.mejo.2024.106124
Xie XGu PDing YNiu DZheng HXie Y(2023)MPU: Memory-centric SIMT Processor via In-DRAM Near-bank ComputingACM Transactions on Architecture and Code Optimization10.1145/360311320:3(1-26)Online publication date: 19-Jul-2023
https://dl.acm.org/doi/10.1145/3603113
Show More Cited By

Index Terms

A Case for Intelligent RAM
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

Index terms have been assigned to the content through auto-classification.

Recommendations

A case study on the application of real phase-change RAM to main memory subsystem
DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe

Phase-change RAM (PCM) has the advantages of better scaling and non-volatility compared with the DRAM which is expected to face its scaling limit in the near future. There have been many studies on applying the PCM to main memory in order to complement ...
Use ECP, not ECC, for hard failures in resistive memories
ISCA '10

As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunately, current error correction techniques are poorly suited to this ...
Preventing PCM banks from seizing too much power
MICRO-44: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

Widespread adoption of Phase Change Memory (PCM) requires solutions to several problems recently addressed in the literature, including limited endurance, increased write latencies, and system-level changes required to exploit non-volatility. One ...

Comments

Information & Contributors

Information

Published In

cover image IEEE Micro

IEEE Micro Volume 17, Issue 2

March 1997

146 pages

ISSN:0272-1732

Issue’s Table of Contents

Copyright © Copyright © 1997 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 March 1997

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

225
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 10 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Li CZhou ZWang YYang FCao TYang MLiang YSun GTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)PIM-DL: Expanding the Applicability of Commodity DRAM-PIMs for Deep Learning via Algorithm-System Co-OptimizationProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640376(879-896)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620665.3640376
Li XGao MRen ZYu KLu WDai CHu WPeng CWu X(2024)A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MACMicroelectronics Journal10.1016/j.mejo.2024.106124145:COnline publication date: 1-Mar-2024
https://dl.acm.org/doi/10.1016/j.mejo.2024.106124
Xie XGu PDing YNiu DZheng HXie Y(2023)MPU: Memory-centric SIMT Processor via In-DRAM Near-bank ComputingACM Transactions on Architecture and Code Optimization10.1145/360311320:3(1-26)Online publication date: 19-Jul-2023
https://dl.acm.org/doi/10.1145/3603113
Lim CLee SChoi JLee JPark SKim HLee JKim Y(2023)Design and Analysis of a Processing-in-DIMM Join Algorithm: A Case Study with UPMEM DIMMsProceedings of the ACM on Management of Data10.1145/35892581:2(1-27)Online publication date: 20-Jun-2023
https://dl.acm.org/doi/10.1145/3589258
Wang ZLiu CArora AJohn LNowatzki TAamodt TJerger NSwift M(2023)Infinity Stream: Portable and Programmer-Friendly In-/Near-Memory FusionProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582032(359-375)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3582016.3582032
Liu RZhang XXie ZWang XLi ZChen XHan YTang M(2023)FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory ComputingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.323373642:9(2889-2902)Online publication date: 1-Sep-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3233736
Liu ZXie ZDong WYuan MYou HLi D(2023)A heterogeneous processing-in-memory approach to accelerate quantum chemistry simulationParallel Computing10.1016/j.parco.2023.103017116:COnline publication date: 1-Jul-2023
https://dl.acm.org/doi/10.1016/j.parco.2023.103017
Shahroodi TWong SHamdioui S(2023)A Case for Genome Analysis Where Genomes ResideEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-031-46077-7_30(453-458)Online publication date: 2-Jul-2023
https://dl.acm.org/doi/10.1007/978-3-031-46077-7_30
Goswami BSuri MTeuscher CHan J(2022)Single Cycle XOR (SCXOR) and Stateful n-bit Parallel Adder Implementation Using 2D RRAM CrossbarProceedings of the 17th ACM International Symposium on Nanoscale Architectures10.1145/3565478.3572329(1-6)Online publication date: 7-Dec-2022
https://dl.acm.org/doi/10.1145/3565478.3572329
Rafique MZhu Z(2022)Dynamic Page Policy Using Perceptron LearningProceedings of the 2022 International Symposium on Memory Systems10.1145/3565053.3565055(1-11)Online publication date: 3-Oct-2022
https://dl.acm.org/doi/10.1145/3565053.3565055
Show More Cited By

View Options

View options

Media

Figures

Other

Tables

View Issue’s Table of Contents