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IBM's S/390 G5 Microprocessor Design

Published: 01 March 1999 Publication History
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  • Abstract

    The S/390 G5, the latest generation IBM mainframe system, more than doubles the performance of its predecessor. The microprocessor used in the system is a sophisticated CISC processor that features a large cache and a very high clock frequency to achieve excellent performance. We discuss the microarchitecture of the processor followed by a description of how this processor is integrated into the system. Finally, we consider the state-of-the-art reliability and availability features that make this mainframe system unique.

    References

    [1]
    Enterprise Systems Architecture/390 Principles of Operation, order number SA22-7201, available through IBM branch offices.
    [2]
    G.S. Rao, et al., "IBM S/390 Parallel Enterprise Servers G3 and G4," IBM J. Research and Development, Vol. 41, No. 4 /5, July/Sept. 1997, pp. 397-403.
    [3]
    C.F. Webb and J.S. Liptay, "A High-Frequency Custom CMOS S/390 Microprocessor," IBM J. Research and Development, Vol. 41, No. 4 /5, July/Sept. 1997, pp. 463-473.
    [4]
    C.F. Webb, et al., "A 400 MHz S/390 Microprocessor," IEEE J. Solid-State Circuits, Vol. 32, No. 11, Nov. 1997, pp. 1,665-1,675.
    [5]
    T.J. Slegel, et al., "IBM S/390 G5 Microprocessor," Hot Chips 10 Conf. Record, Aug. 1998 (copies available from the author).
    [6]
    R.M. Averill III, et al., "Deep Submicron Design Techniques for the 500 MHz IBM S/390 G5 Custom Microprocessor," Proc. Int'l Conf. Computer Design, IEEE Computer Soc. Press, Los Alamitos, Calif., Oct. 1998.
    [7]
    Large Systems Performance Reference, order number SC28-1187, available through IBM branch offices.
    [8]
    K. Hua, et al., "Early Resolution of Address Translation in Cache Design," Proc. Int'l Conf. Computer Eng., Sept. 1990.
    [9]
    E.M. Schwarz L. Sigal and T.J. McPherson, "CMOS Floating-Point Unit for the S/390 Parallel Enterprise Server G4," IBM J. Research and Development, Vol. 41, No. 4 /5, July/Sept. 1997, pp. 475-488.
    [10]
    E.M. Schwarz R.M. Smith and C.A. Krygowski, "The S/390 G5 Floating-point Unit Supporting Hex and Binary Architectures," Proc. 14th IEEE Symp. Computer Arithmetic, to be published by IEEE Computer Soc. Press, Los Alamitos, Calif., Apr. 1999.

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      Published In

      cover image IEEE Micro
      IEEE Micro  Volume 19, Issue 2
      March 1999
      154 pages

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      IEEE Computer Society Press

      Washington, DC, United States

      Publication History

      Published: 01 March 1999

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      • (2020)Predictive Reliability and Fault Management in Exascale SystemsACM Computing Surveys10.1145/340395653:5(1-32)Online publication date: 28-Sep-2020
      • (2019)Architectural Support for Containment-based SecurityProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3297858.3304020(361-377)Online publication date: 4-Apr-2019
      • (2018)Core ReliabilityIEEE Computer Architecture Letters10.1109/LCA.2018.279143317:2(105-108)Online publication date: 1-Jul-2018
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