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The MAP1000A VLIW Mediaprocessor

Published: 01 March 2000 Publication History

Abstract

This alternate to using custom ASICs for each multimedia-processing task is a single-chip, programmable mediaprocessor that also makes use of general-purpose RISC processing and a VLIW framework.

References

[1]
C. Basoglu, et al., "Parallel Image Computing in Modern Commercially-Available Processors," Int'l J. Imaging Systems, Vol. 9, 1998, pp. 407-415.
[2]
J. Turley, "Multimedia Chips Complicate Choices," Microprocessor Report, Vol. 10, No. 2, 1996, pp. 14-19.
[3]
R.P. Colwell, et al., "A VLIW Architecture for a Trace Scheduling Compiler," IEEE Trans. on Computers, Vol. 37, 1988, pp. 967-979.
[4]
S.S. Muchnick, Advanced Compiler Design and Implementation, Morgan Kaufmann, San Francisco, Calif., 1997.
[5]
A.V. Aho R. Sethi and J.D. Ullman, Compilers Principles, Techniques and Tools, Addison-Wesley, Reading, Mass., 1986.
[6]
W. Lee and C. Basoglu, "MPEG-2 Decoder Implementation on MAP1000A Mediaprocessor Using the C Language," SPIE Proc. Media Processors 2000, Vol. 3970, 2000, pp. 27-36.
[7]
I. Stotland D. Kim and Y. Kim, "Image Computing Library for a Next-Generation VLIW Multimedia Processor," SPIE Proc. Electronic Imaging, Vol. 3655, 1999, pp. 47-58.
[8]
R. Gov, et al., "Next-Generation Media Processors and Their Impact on Medical Imaging," SPIE Proc. Medical Imaging Conf., 1998, pp. 271-278.
[9]
P.G. Lowney, et al., "The Multiflow Trace Scheduling Compiler," The J. of Supercomputing, Vol. 7, 1993, pp. 51-142.

Cited By

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  • (2018)Data Cache and Direct Memory Access in Programming MediaprocessorsIEEE Micro10.1109/40.94667821:4(33-42)Online publication date: 29-Dec-2018

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Published In

cover image IEEE Micro
IEEE Micro  Volume 20, Issue 2
March 2000
86 pages

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 March 2000

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  • (2018)Data Cache and Direct Memory Access in Programming MediaprocessorsIEEE Micro10.1109/40.94667821:4(33-42)Online publication date: 29-Dec-2018

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