research-article

Cached DRAM for ILP Processor Memory Access Latency Reduction

Authors:

Zhao Zhang,

Zhichun Zhu,

Xiaodong ZhangAuthors Info & Claims

IEEE Micro, Volume 21, Issue 4

Pages 22 - 32

https://doi.org/10.1109/40.946676

Published: 01 July 2001 Publication History

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Abstract

Cached DRAM adds a small cache onto a DRAM chip to reduce average DRAM access latency. The authors compare cached DRAM with other advanced dram techniques for reducing memory access latency in instruction-level-parallelism processors.

References

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Cited By

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Shin WJang JChoi JSuh JKim L(2017)Bank-Group Level ParallelismIEEE Transactions on Computers10.1109/TC.2017.266547566:8(1428-1434)Online publication date: 1-Aug-2017
https://dl.acm.org/doi/10.1109/TC.2017.2665475
Alves MSantos PMoreira FDiener MCarro LIyer RGarg S(2015)Saving memory movements through vector processing in the DRAMProceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.5555/2830689.2830705(117-126)Online publication date: 4-Oct-2015
https://dl.acm.org/doi/10.5555/2830689.2830705
Chen KLi SAhn JMuralimanohar NZhao JXu CO SXie YBrockman JJouppi NBhuyan LChong FSarkar V(2015)History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM ArchitecturesProceedings of the 29th ACM on International Conference on Supercomputing10.1145/2751205.2751227(251-261)Online publication date: 8-Jun-2015
https://dl.acm.org/doi/10.1145/2751205.2751227
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Index Terms

Cached DRAM for ILP Processor Memory Access Latency Reduction
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

Index terms have been assigned to the content through auto-classification.

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Published In

IEEE Micro Volume 21, Issue 4

July 2001

57 pages

ISSN:0272-1732

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 July 2001

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Shin WJang JChoi JSuh JKim L(2017)Bank-Group Level ParallelismIEEE Transactions on Computers10.1109/TC.2017.266547566:8(1428-1434)Online publication date: 1-Aug-2017
https://dl.acm.org/doi/10.1109/TC.2017.2665475
Alves MSantos PMoreira FDiener MCarro LIyer RGarg S(2015)Saving memory movements through vector processing in the DRAMProceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.5555/2830689.2830705(117-126)Online publication date: 4-Oct-2015
https://dl.acm.org/doi/10.5555/2830689.2830705
Chen KLi SAhn JMuralimanohar NZhao JXu CO SXie YBrockman JJouppi NBhuyan LChong FSarkar V(2015)History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM ArchitecturesProceedings of the 29th ACM on International Conference on Supercomputing10.1145/2751205.2751227(251-261)Online publication date: 8-Jun-2015
https://dl.acm.org/doi/10.1145/2751205.2751227
Yoon HMeza JMuralimanohar NJouppi NMutlu O(2014)Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change MemoriesACM Transactions on Architecture and Code Optimization10.1145/266936511:4(1-25)Online publication date: 8-Dec-2014
https://dl.acm.org/doi/10.1145/2669365
Wang JDong XXie Y(2014)Building and Optimizing MRAM-Based Commodity MemoriesACM Transactions on Architecture and Code Optimization10.1145/266710511:4(1-22)Online publication date: 8-Dec-2014
https://dl.acm.org/doi/10.1145/2667105
Son YSeongil ORo YLee JAhn J(2013)Reducing memory access latency with asymmetric DRAM bank organizationsACM SIGARCH Computer Architecture News10.1145/2508148.248595541:3(380-391)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2508148.2485955
Son YSeongil ORo YLee JAhn JMendelson A(2013)Reducing memory access latency with asymmetric DRAM bank organizationsProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485955(380-391)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2485922.2485955
Woo DSeong NLee H(2013)Pragmatic integration of an SRAM row cache in heterogeneous 3-D DRAM architecture using TSVIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217676121:1(1-13)Online publication date: 1-Jan-2013
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Kim YSeshadri VLee DLiu JMutlu OLu STorrellas J(2012)A case for exploiting subarray-level parallelism (SALP) in DRAMProceedings of the 39th Annual International Symposium on Computer Architecture10.5555/2337159.2337202(368-379)Online publication date: 9-Jun-2012
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Kim YSeshadri VLee DLiu JMutlu O(2012)A case for exploiting subarray-level parallelism (SALP) in DRAMACM SIGARCH Computer Architecture News10.1145/2366231.233720240:3(368-379)Online publication date: 9-Jun-2012
https://dl.acm.org/doi/10.1145/2366231.2337202
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Cited By

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Software and hardware methods for memory access latency reduction on ilp processors

Reducing memory access latency with asymmetric DRAM bank organizations

Reducing memory access latency with asymmetric DRAM bank organizations

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