research-article

Electrical analysis and modeling of floating-gate fault

Authors:

M. Renovell,

G. N. CambonAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 11, Issue 11

Pages 1450 - 1458

https://doi.org/10.1109/43.177407

Published: 01 November 2006 Publication History

Abstract

It is demonstrated that a floating gate transistor (FGT) is influenced by its topological environment. The equivalent gate-to-source voltage of the FGT depends on the initial charges trapped in the gate oxide, the surrounding potential of metal lines and the drain-to-source voltage of the FGT itself. An electrical study of the floating gate fault is presented. A theoretical model taking into account the influence of the transistor's environment is proposed. Analytical expressions for the equivalent gate-to-source voltage are derived, and the FGTs electrical operation mode is analyzed. This model is validated by SPICE simulations and by actual device measurements. The problem of testing for FGTs is discussed

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Forero FChampac VRenovell M(2022)B-open Defect: A Novel Defect Model in FinFET TechnologyACM Journal on Emerging Technologies in Computing Systems10.1145/356424419:1(1-19)Online publication date: 9-Dec-2022
https://dl.acm.org/doi/10.1145/3564244
Pomeranz I(2019)Incomplete Tests for Undetectable Faults to Improve Test Set QualityACM Transactions on Design Automation of Electronic Systems10.1145/330649324:2(1-13)Online publication date: 13-Feb-2019
https://dl.acm.org/doi/10.1145/3306493
Pomeranz I(2017)A bridging fault model for line coverage in the presence of undetected transition faultsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130603(938-941)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130603
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 11, Issue 11

November 2006

142 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Forero FChampac VRenovell M(2022)B-open Defect: A Novel Defect Model in FinFET TechnologyACM Journal on Emerging Technologies in Computing Systems10.1145/356424419:1(1-19)Online publication date: 9-Dec-2022
https://dl.acm.org/doi/10.1145/3564244
Pomeranz I(2019)Incomplete Tests for Undetectable Faults to Improve Test Set QualityACM Transactions on Design Automation of Electronic Systems10.1145/330649324:2(1-13)Online publication date: 13-Feb-2019
https://dl.acm.org/doi/10.1145/3306493
Pomeranz I(2017)A bridging fault model for line coverage in the presence of undetected transition faultsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130603(938-941)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130603
Moreno JRenovell MChampac V(2016)Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process VariationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239793424:1(378-382)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2397934
Pomeranz IReddy SLombardi FBhanja SMassoud YBahar R(2009)Partitioned n-detection test generationProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531566(93-98)Online publication date: 10-May-2009
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Reddy SPomeranz ILiu CFix L(2008)On tests to detect via opens in digital CMOS circuitsProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391682(840-845)Online publication date: 8-Jun-2008
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Ghosh SJoel Ferguson F(2005)Detection probabilities of interconnect breaksIntegration, the VLSI Journal10.5555/1062115.171208138:3(451-465)Online publication date: 1-Jan-2005
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Ghosh SFerguson FGarrett DLach JZukowski C(2004)Estimating detection probability of interconnect opens using stuck-at testsProceedings of the 14th ACM Great Lakes symposium on VLSI10.1145/988952.989014(254-259)Online publication date: 26-Apr-2004
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Pronath MGraeb HAntreich K(2002)A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated CircuitsProceedings of the conference on Design, automation and test in Europe10.5555/882452.874365Online publication date: 4-Mar-2002
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Hashizume MIchimiya MYotsuyanagi HTamesada T(2001)CMOS open defect detection by supply current testProceedings of the conference on Design, automation and test in Europe10.5555/367072.367358Online publication date: 13-Mar-2001
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Modelling of direct tunneling gate leakage current of floating-gate CMOS transistor in sub 100 nm technologies

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Electrical model of the floating gate defect in CMOS ICs: implications on I_DDQ testing