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View all- Forero FChampac VRenovell M(2022)B-open Defect: A Novel Defect Model in FinFET TechnologyACM Journal on Emerging Technologies in Computing Systems10.1145/356424419:1(1-19)Online publication date: 16-Sep-2022
An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances ...
This paper explores the effectiveness of dual-Vt design under aggressive scaling of technology, which results in significant increase in all components of leakage (subthreshold, gate and junction tunneling) while having large variations in process ...
In this paper, the potential of Tunnel FETs (TFETs) for ultra-low power operation is investigated in the context of digital circuits operating below 500 mV. A comparative analysis of TFETs and SOI CMOS in 32 nm technology is performed through device- ...
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