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Sehwa: a software package for synthesis of pipelines from behavioral specifications

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N. Park,

A. C. ParkerAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 7, Issue 3

Pages 356 - 370

https://doi.org/10.1109/43.3169

Published: 01 November 2006 Publication History

Abstract

A set of techniques for the synthesis of pipelined data paths is described, and Sehwa, a program that performs such synthesis, is presented. The task includes the generation of data paths from a data-flow graph along with a clocking scheme that overlaps execution of multiple tasks. Some design examples are given. Sehwa can find the minimum-cost design, the highest performance design, and other designs between these two in the design space. Sehwa is written in Franz Lisp and executes within minutes, for problems of practical size, on a VAX 11/750

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Prihozhy ACasale-Brunet SBezati EMattavelli M(2020)Pipeline Synthesis and Optimization from Branched Feedback Dataflow ProgramsJournal of Signal Processing Systems10.1007/s11265-020-01568-592:10(1091-1099)Online publication date: 1-Oct-2020
https://dl.acm.org/doi/10.1007/s11265-020-01568-5
Zhang ZLiu BHenkel J(2013)SDC-based modulo scheduling for pipeline synthesisProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561872(211-218)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561872
Fernando PKatkoori SKeymeulen DZebulum RStoica A(2010)Customizable FPGA IP core implementation of a general-purpose genetic algorithm engineIEEE Transactions on Evolutionary Computation10.1109/TEVC.2009.202503214:1(133-149)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TEVC.2009.2025032
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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 7, Issue 3

November 2006

108 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Prihozhy ACasale-Brunet SBezati EMattavelli M(2020)Pipeline Synthesis and Optimization from Branched Feedback Dataflow ProgramsJournal of Signal Processing Systems10.1007/s11265-020-01568-592:10(1091-1099)Online publication date: 1-Oct-2020
https://dl.acm.org/doi/10.1007/s11265-020-01568-5
Zhang ZLiu BHenkel J(2013)SDC-based modulo scheduling for pipeline synthesisProceedings of the International Conference on Computer-Aided Design10.5555/2561828.2561872(211-218)Online publication date: 18-Nov-2013
https://dl.acm.org/doi/10.5555/2561828.2561872
Fernando PKatkoori SKeymeulen DZebulum RStoica A(2010)Customizable FPGA IP core implementation of a general-purpose genetic algorithm engineIEEE Transactions on Evolutionary Computation10.1109/TEVC.2009.202503214:1(133-149)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TEVC.2009.2025032
Ashouei MChatterjee A(2009)Checksum-based probabilistic transient-error compensation for linear digital systemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200458717:10(1447-1460)Online publication date: 1-Oct-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2004587
Libby JKent K(2009)A Methodology for Rapid Optimization of HandelC SpecificationsProceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping10.1109/RSP.2009.31(81-87)Online publication date: 23-Jun-2009
https://dl.acm.org/doi/10.1109/RSP.2009.31
Kam TKishinevsky MCortadella JGalceran-Oms MNassif SRoychowdhury J(2008)Correct-by-construction microarchitectural pipeliningProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509558(434-441)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509558
Fan KKudlur MPark HMahlke SBergamaschi RChoi K(2006)Increasing hardware efficiency with multifunction loop acceleratorsProceedings of the 4th international conference on Hardware/software codesign and system synthesis10.1145/1176254.1176322(276-281)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176254.1176322
Cordone RFerrandi FSantambrogio MPalermo GSciuto DHirose F(2006)Using speculative computation and parallelizing techniques to improve scheduling of control based designsProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118502(898-904)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118502
Sun WWirthlin MNeuendorffer SWilton SDeHon A(2006)Combining module selection and resource sharing for efficient FPGA pipeline synthesisProceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays10.1145/1117201.1117228(179-188)Online publication date: 22-Feb-2006
https://dl.acm.org/doi/10.1145/1117201.1117228
Fan KKudlur MPark HMahlke S(2005)Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis SystemProceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2005.17(219-232)Online publication date: 12-Nov-2005
https://dl.acm.org/doi/10.1109/MICRO.2005.17
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Sehwa: a program for synthesis of pipelines

Sehwa: A program for synthesis of pipelines

System Synthesis with VHDL: A Transformational Approach

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