Strategy for electromagnetic interconnect modeling

In this tutorial we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due to increasing operating frequencies, microwave-like effects will become important. Therefore ...

With fast switching speeds and large interconnect trees (MCMs), the resistance and inductance of interconnect has a dominant impact on logic gate delay. In this paper, we propose a new PI model for distributed RC and RLC interconnects to estimate the ...

In deep submicron designs, predicting gate slews and delays for interconnect loads is vitally important for Static Timing Analysis (STA). The effective capacitance C_eff concept is usually used to calculate the gate delay of interconnect loads. Many C_eff ...