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SPICE models for flicker noise in p-MOSFETs in the saturation region

Published: 01 November 2006 Publication History

Abstract

The number fluctuation theory based on the McWhorter's charge-trapping model and the bulk mobility fluctuation theory based on Hooge's hypothesis are the two major existing theories to explain the origins of the flicker noise, which is the dominant low-frequency noise source in silicon metal-oxide-semiconductor field-effect transistors (MOSFETs). We have done the flicker noise measurements and SPICE simulations for both long-channel (5 μm) and short-channel (1.2 μm and 0.6 μm) p-type channel metal-oxide-semiconductor (PMOS) transistors. HSPICE [device model: level 3, level 46 (BSIM 3v2) and level 47 (BSIM 3v3); noise model: NLEV=0 and NLEV=2 and 3] and PSPICE [device model: level 3, level 6 (BSIM 3v2) and level 7 (BSIM 3v3); noise model: NLEV=0 and NLEV=2 and 3] were used for the simulations. Our measurement results suggest that in the saturation region, for long-channel PMOS transistors, the flicker noise is due to the bulk effect and it follows the mobility fluctuation theory, while for short-channel ones, it is due to the surface state effect and the number fluctuation theory applies. Our simulation results showed that for both HSPICE and PSPICE, level 3 and NLEV=0 are the appropriate models for the simulations of long-channel PMOS transistor flicker noise; HSPICE with level 47 or 49 and NLEV=2 and 3 and PSPICE with level 6 and NLEV=2 and 3 are applied for the short-channel PMOS devices. The simulation results are consistent with the measurements

Cited By

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  • (2015)The i-v characteristic prediction of BCD LV pMOSFET devices based on an ANFIS-Based methodologyAdvances in Fuzzy Systems10.1155/2015/8245242015(4-4)Online publication date: 1-Jan-2015
  • (2008)Figure-of-merit-based area-constrained design of differential amplifiersVLSI Design10.1155/2008/8479322008:2(1-5)Online publication date: 1-Jan-2008
  • (2006)Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS DesignAnalog Integrated Circuits and Signal Processing10.1007/s10470-006-2949-y47:2(137-163)Online publication date: 1-May-2006

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 20, Issue 6
November 2006
105 pages

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IEEE Press

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Published: 01 November 2006

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Cited By

View all
  • (2015)The i-v characteristic prediction of BCD LV pMOSFET devices based on an ANFIS-Based methodologyAdvances in Fuzzy Systems10.1155/2015/8245242015(4-4)Online publication date: 1-Jan-2015
  • (2008)Figure-of-merit-based area-constrained design of differential amplifiersVLSI Design10.1155/2008/8479322008:2(1-5)Online publication date: 1-Jan-2008
  • (2006)Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS DesignAnalog Integrated Circuits and Signal Processing10.1007/s10470-006-2949-y47:2(137-163)Online publication date: 1-May-2006

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