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A communication architecture tailored for analog VLSI artificial neural networks: intrinsic performance and limitations

Published: 01 May 1994 Publication History

Abstract

An architecture for interchip communication among analog VLSI neural networks is proposed. Activity is encoded in a neuron's pulse emission frequency. Information is transmitted through the non-arbitered, asynchronous access of pulses to a common bus. The impact of collisions when the bus is accessed by more than one user is investigated. The information-carrying capability is assessed and the trade-off between accuracy of the transmitted information and attainable dynamic range is brought out in terms of simple global parameters that characterize the application. It is found that the proposed architecture is well suited for the kind of communication requirements associated to neural computation systems. A coding scheme aimed at pushing the system towards its theoretical performance is also presented and evaluated

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        cover image IEEE Transactions on Neural Networks
        IEEE Transactions on Neural Networks  Volume 5, Issue 3
        May 1994
        189 pages

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        IEEE Press

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        Published: 01 May 1994

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