research-article

A physical design tool for built-in self-repairable RAMs

Authors:

Anurag GuptaAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 9, Issue 2

Pages 352 - 364

https://doi.org/10.1109/92.924057

Published: 01 April 2001 Publication History

Abstract

In this paper, we present the description and evaluation of a novel physical design tool, BISRAMGEN, that can generate reconfigurable and fault-tolerant RAM modules. This tool designs a redundant RAM array with accompanying built-in self-test (BIST) and built-in self-repair (BISR) logic that can switch out faulty rows and switch in spare rows. Built-in self-repair causes significant improvement in reliability, production yield, and manufacturing cost of ASICs and microprocessors with embedded RAMs.

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Wang LPatel N(2019)Improving error tolerance for multithreaded register filesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515827.151583416:8(1009-1020)Online publication date: 21-Nov-2019
https://dl.acm.org/doi/10.5555/1515827.1515834
Chakraborty K(2019)Testing and Reliability Techniques for High-Bandwidth Embedded RAMsJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000009316.94309.6620:1(89-108)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1023/B%3AJETT.0000009316.94309.66
Li JTseng THou C(2018)Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202236318:9(1361-1366)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2009.2022363
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Index Terms

A physical design tool for built-in self-repairable RAMs
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
2. Hardware

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 9, Issue 2

April 2001

177 pages

ISSN:1063-8210

Editor:
Eby G. Friedman
Univ. of Rochester, Rochester, NY

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IEEE Educational Activities Department

United States

Publication History

Published: 01 April 2001

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Cited By

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Wang LPatel N(2019)Improving error tolerance for multithreaded register filesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515827.151583416:8(1009-1020)Online publication date: 21-Nov-2019
https://dl.acm.org/doi/10.5555/1515827.1515834
Chakraborty K(2019)Testing and Reliability Techniques for High-Bandwidth Embedded RAMsJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000009316.94309.6620:1(89-108)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1023/B%3AJETT.0000009316.94309.66
Li JTseng THou C(2018)Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202236318:9(1361-1366)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2009.2022363
Wang SWang L(2009)Exploiting memory soft redundancy for joint improvement of error tolerance and access efficiencyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200174317:8(973-982)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2001743
Wang SWang LHassoun S(2006)Exploiting soft redundancy for error-resilient on-chip memory designProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233610(535-540)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233610
Wang L(2005)Error-tolerance memory Microarchitecture via Dynamic MultithreadingProceedings of the 2005 International Conference on Computer Design10.1109/ICCD.2005.50(179-184)Online publication date: 2-Oct-2005
https://dl.acm.org/doi/10.1109/ICCD.2005.50

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A physical design tool for built-in self-repairable static RAMs

Built-in self-repair schemes for flash memories

Built-In Testing of Memory Using an On-Chip Compact Testing Scheme

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