research-article

Quantifying and enhancing power awareness of VLSI systems

Authors:

Manish Bhardwaj,

Anantha P. ChandrakasanAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 9, Issue 6

Pages 757 - 772

https://doi.org/10.1109/92.974890

Published: 01 December 2001 Publication History

Abstract

An increasingly important figure-of-merit of a VLSI system is "power awareness," which is its ability to scale power consumption in response to changing operating conditions. These changes might be brought about by the time-varying nature of inputs, desired output quality, or just environmental conditions. Regardless of whether they were engineered for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that some systems are "more" power aware than others. Equivalently, we should be able to re-engineer systems to increase their power awareness. In this paper, we attempt to quantitatively define power awareness and how such awareness can be enhanced using a systematic technique. We illlustrate this technique by applying it to VLSI systems at several levels of the system hierarchy--- multipliers, register files, digital filters, dynamic voltage-scaled processors, and data-gathering wireless networks. It is seen that, as a result, the power awareness of these preceding systems can be significantly enhanced leading to increases in battery lifetimes in the range of 60 - 200%.

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Cited By

Yin HJia HZhou JGao Z(2017)Survey on Algorithm and VLSI Architecture for MPEG-Like Video CoderJournal of Signal Processing Systems10.1007/s11265-016-1160-388:3(357-410)Online publication date: 1-Sep-2017
https://dl.acm.org/doi/10.1007/s11265-016-1160-3
Chen CHung CHuang Y(2010)An energy-efficient partial FFT processor for the OFDMA communication systemIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2010.204031857:2(136-140)Online publication date: 1-Feb-2010
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Lin CHuang PWu B(2010)An Efficient Pipeline Architecture and Memory Bit-Width Analysis for Discrete Wavelet Transform of the 9/7 Filter for JPEG 2000Journal of Signal Processing Systems10.1007/s11265-009-0375-y59:3(245-253)Online publication date: 1-Jun-2010
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Index Terms

Quantifying and enhancing power awareness of VLSI systems
1. Hardware
  1. Very large scale integration design

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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 9, Issue 6

System Level Design

12/1/2001

261 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 2001.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 December 2001

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Cited By

Yin HJia HZhou JGao Z(2017)Survey on Algorithm and VLSI Architecture for MPEG-Like Video CoderJournal of Signal Processing Systems10.1007/s11265-016-1160-388:3(357-410)Online publication date: 1-Sep-2017
https://dl.acm.org/doi/10.1007/s11265-016-1160-3
Chen CHung CHuang Y(2010)An energy-efficient partial FFT processor for the OFDMA communication systemIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2010.204031857:2(136-140)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TCSII.2010.2040318
Lin CHuang PWu B(2010)An Efficient Pipeline Architecture and Memory Bit-Width Analysis for Discrete Wavelet Transform of the 9/7 Filter for JPEG 2000Journal of Signal Processing Systems10.1007/s11265-009-0375-y59:3(245-253)Online publication date: 1-Jun-2010
https://dl.acm.org/doi/10.1007/s11265-009-0375-y
Chen YChen TTsai CTsai SChen L(2009)Algorithm and architecture design of power-oriented H.264/AVC baseline profile encoder for portable devicesIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2009.202032319:8(1118-1128)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TCSVT.2009.2020323
Abderazek BYoshinaga TSowa M(2006)High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor CoreThe Journal of Supercomputing10.1007/s11227-006-6719-538:1(3-15)Online publication date: 1-Oct-2006
https://dl.acm.org/doi/10.1007/s11227-006-6719-5
Calhoun BDaly DVerma NFinchelstein DWentzloff DWang ACho SChandrakasan A(2005)Design Considerations for Ultra-Low Energy Wireless Microsensor NodesIEEE Transactions on Computers10.1109/TC.2005.9854:6(727-740)Online publication date: 1-Jun-2005
https://dl.acm.org/doi/10.1109/TC.2005.98
Lee H(2005)Reconfigurable power-aware scalable booth multiplierProceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I10.1007/11552413_26(176-183)Online publication date: 14-Sep-2005
https://dl.acm.org/doi/10.1007/11552413_26
Shih ECho SLee FCalhoun BChandrakasan A(2004)Design Considerations for Energy-Efficient Radios in Wireless Microsensor NetworksJournal of VLSI Signal Processing Systems10.5555/971216.281348837:1(77-94)Online publication date: 1-May-2004
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Wang AChandrakasan AVerbauwhede IRoh H(2003)Energy-aware architectures for a real-valued FFT implementationProceedings of the 2003 international symposium on Low power electronics and design10.1145/871506.871598(360-365)Online publication date: 25-Aug-2003
https://dl.acm.org/doi/10.1145/871506.871598
Di JYuan JStan MGarrett DNakajima K(2003)Power-aware pipelined multiplier design based on 2-dimensional pipeline gatingProceedings of the 13th ACM Great Lakes symposium on VLSI10.1145/764808.764826(64-67)Online publication date: 28-Apr-2003
https://dl.acm.org/doi/10.1145/764808.764826

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