article

High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core

Authors:

Ben A. Abderazek,

Tsutomu Yoshinaga,

Masahiro SowaAuthors Info & Claims

The Journal of Supercomputing, Volume 38, Issue 1

Pages 3 - 15

https://doi.org/10.1007/s11227-006-6719-5

Published: 01 October 2006 Publication History

Abstract

Emerging high-level hardware description and synthesis technologies in conjunction with field programmable gate arrays (FPGAs) have significantly lowered the threshold for hardware development. Opportunities exist to integrate these technologies into a tool for exploring and evaluating microarchitectural designs especially for newly proposed architectures. This paper presents a prototyping of a new processor core based on Queue architecture as starting point for application-specific processor design exploration. Using a hardware description language, we have created the Synthesizable model of a produced order parallel queue processor core for the integer subset parallel Queue architecture. A prototype implementation is produced by synthesizing the high-level model for the Stratix FPGA prototyping board. We show how to perform prototyping and optimizations to fully exploit the capabilities of the prototyped Queue processor core, while maintaining a common source base.

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Cited By

Abderazek BMasuda MCanedo AKuroda K(2011)Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architectureThe Journal of Supercomputing10.1007/s11227-010-0409-z57:3(314-338)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1007/s11227-010-0409-z
Canedo AAbderazek BSowa M(2010)Compiling for Reduced Bit-Width Queue ProcessorsJournal of Signal Processing Systems10.1007/s11265-008-0286-359:1(45-55)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s11265-008-0286-3
Fernandes SOliveira BSilva ISaraiva IRibas RPlett C(2009)Using NoC routers as processing elementsProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601927(1-6)Online publication date: 31-Aug-2009
https://dl.acm.org/doi/10.1145/1601896.1601927
Show More Cited By

Index Terms

High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core
1. Computer systems organization
  1. Architectures
    1. Other architectures
2. Hardware

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Published In

cover image The Journal of Supercomputing

The Journal of Supercomputing Volume 38, Issue 1

October 2006

103 pages

ISSN:0920-8542

Issue’s Table of Contents

Copyright © Copyright © 2006 Springer Science + Business Media, LLC.

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 October 2006

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Cited By

Abderazek BMasuda MCanedo AKuroda K(2011)Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architectureThe Journal of Supercomputing10.1007/s11227-010-0409-z57:3(314-338)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1007/s11227-010-0409-z
Canedo AAbderazek BSowa M(2010)Compiling for Reduced Bit-Width Queue ProcessorsJournal of Signal Processing Systems10.1007/s11265-008-0286-359:1(45-55)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s11265-008-0286-3
Fernandes SOliveira BSilva ISaraiva IRibas RPlett C(2009)Using NoC routers as processing elementsProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601927(1-6)Online publication date: 31-Aug-2009
https://dl.acm.org/doi/10.1145/1601896.1601927
Canedo AAbderazek BSowa M(2009)Compiler Support for Code Size Reduction Using a Queue-Based ProcessorTransactions on High-Performance Embedded Architectures and Compilers II10.1007/978-3-642-00904-4_14(269-285)Online publication date: 22-Apr-2009
https://dl.acm.org/doi/10.1007/978-3-642-00904-4_14
Akanda MAbderazek BSowa M(2008)Dual-execution mode processor architectureThe Journal of Supercomputing10.1007/s11227-007-0151-344:2(103-125)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1007/s11227-007-0151-3
Canedo AAbderazek BSowa M(2007)An efficient code generation algorithm for code size reduction using 1-offset P-code queue computation modelProceedings of the 2007 international conference on Embedded and ubiquitous computing10.5555/1780745.1780768(196-208)Online publication date: 17-Dec-2007
https://dl.acm.org/doi/10.5555/1780745.1780768

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