article

Partitioning Methodology for Heterogeneous Reconfigurable Functional Units

Authors:

Michalis D. Galanis,

Gregory Dimitroulakos,

Costas E. GoutisAuthors Info & Claims

The Journal of Supercomputing, Volume 38, Issue 1

Pages 17 - 34

https://doi.org/10.1007/s11227-006-6743-5

Published: 01 October 2006 Publication History

Abstract

A partitioning methodology between the reconfigurable hardware blocks of different granularity, which are embedded in a generic heterogeneous architecture, is presented. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by a 2-Dimensional Array of Processing Elements. Critical parts, called kernels, are mapped on the coarse-grain reconfigurable logic for improving performance. The partitioning method is mainly composed by three steps: the analysis of the input code, the mapping onto the Coarse-Grain Reconfigurable Array and the mapping onto the FPGA. The partitioning flow is implemented by a prototype software framework. Analytical partitioning experiments, using five real-world applications, show that the execution time speedup relative to an all-FPGA solution ranges from 1.4 to 5.0.

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Cited By

Yazdinejad ABohlooli AJamshidi K(2018)Efficient design and hardware implementation of the OpenFlow v1.3 Switch on the Virtex-6 FPGA ML605The Journal of Supercomputing10.1007/s11227-017-2175-774:3(1299-1320)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1007/s11227-017-2175-7
Jafri SDaneshtalab MAbbas NLeon GHemani A(2016)TransMapIEEE Transactions on Computers10.1109/TC.2016.252598165:11(3456-3469)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TC.2016.2525981
Dimitroulakos GKostaras NGalanis MGoutis C(2009)Compiler assisted architectural exploration framework for coarse grained reconfigurable arraysThe Journal of Supercomputing10.1007/s11227-008-0208-y48:2(115-151)Online publication date: 1-May-2009
https://dl.acm.org/doi/10.1007/s11227-008-0208-y
Show More Cited By

Index Terms

Partitioning Methodology for Heterogeneous Reconfigurable Functional Units
1. Hardware
  1. Hardware validation
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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cover image The Journal of Supercomputing

The Journal of Supercomputing Volume 38, Issue 1

October 2006

103 pages

ISSN:0920-8542

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Copyright © Copyright © 2006 Springer Science + Business Media, LLC.

Publisher

Kluwer Academic Publishers

United States

Publication History

Published: 01 October 2006

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Cited By

Yazdinejad ABohlooli AJamshidi K(2018)Efficient design and hardware implementation of the OpenFlow v1.3 Switch on the Virtex-6 FPGA ML605The Journal of Supercomputing10.1007/s11227-017-2175-774:3(1299-1320)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1007/s11227-017-2175-7
Jafri SDaneshtalab MAbbas NLeon GHemani A(2016)TransMapIEEE Transactions on Computers10.1109/TC.2016.252598165:11(3456-3469)Online publication date: 1-Nov-2016
https://dl.acm.org/doi/10.1109/TC.2016.2525981
Dimitroulakos GKostaras NGalanis MGoutis C(2009)Compiler assisted architectural exploration framework for coarse grained reconfigurable arraysThe Journal of Supercomputing10.1007/s11227-008-0208-y48:2(115-151)Online publication date: 1-May-2009
https://dl.acm.org/doi/10.1007/s11227-008-0208-y
Dimitroulakos GGalanis MKostaras NGoutis CBanerjee UMoreira JDubois MStenström P(2007)A unified evaluation framework for coarse grained reconfigurable array architecturesProceedings of the 4th international conference on Computing frontiers10.1145/1242531.1242557(161-172)Online publication date: 7-May-2007
https://dl.acm.org/doi/10.1145/1242531.1242557

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