article

Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System

Authors:

Varghese George,

Vandana Prabhu,

Jan RabaeyAuthors Info & Claims

Journal of VLSI Signal Processing Systems, Volume 28, Issue 1-2

Pages 47 - 61

Published: 01 May 2001 Publication History

Abstract

In this paper, we first present a reconfigurable architecture template for low-power digital signal processing, and then an energy conscious design methodology to bridge the algorithm to architecture gap. The energy efficiency of such an architecture and the effectiveness of the methodology are demonstrated in case study implementations targeting baseband voice processing and digital signal processing.

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Cited By

Yang CChen MOrailoglu A(2010)Squashing code size in microcoded IPs while delivering high decompression speedDesign Automation for Embedded Systems10.1007/s10617-010-9057-z14:3(265-284)Online publication date: 1-Sep-2010
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Yang CChen MOrailoglu ARosenstiel WWakabayashi K(2009)Squashing microcode stores to size in embedded systems while delivering rapid microcode accessesProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629471(249-256)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629471
Guha RBagherzadeh NChou P(2009)Resource management and task partitioning and scheduling on a run-time reconfigurable embedded systemComputers and Electrical Engineering10.1016/j.compeleceng.2008.06.00835:2(258-285)Online publication date: 1-Mar-2009
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Index Terms

Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems

Index terms have been assigned to the content through auto-classification.

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Copyright © Copyright © 2001 Kluwer Academic Publishers.

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Published: 01 May 2001

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Cited By

Yang CChen MOrailoglu A(2010)Squashing code size in microcoded IPs while delivering high decompression speedDesign Automation for Embedded Systems10.1007/s10617-010-9057-z14:3(265-284)Online publication date: 1-Sep-2010
https://dl.acm.org/doi/10.1007/s10617-010-9057-z
Yang CChen MOrailoglu ARosenstiel WWakabayashi K(2009)Squashing microcode stores to size in embedded systems while delivering rapid microcode accessesProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629471(249-256)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629471
Guha RBagherzadeh NChou P(2009)Resource management and task partitioning and scheduling on a run-time reconfigurable embedded systemComputers and Electrical Engineering10.1016/j.compeleceng.2008.06.00835:2(258-285)Online publication date: 1-Mar-2009
https://dl.acm.org/doi/10.1016/j.compeleceng.2008.06.008
Karuri KChattopadhyay AChen XKammler DHao LLeupers RMeyr HAscheid G(2008)A design flow for architecture exploration and implementation of partially reconfigurable processorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.5555/1515843.151584716:10(1281-1294)Online publication date: 1-Oct-2008
https://dl.acm.org/doi/10.5555/1515843.1515847
Deledda AMucci CVitkovski ABonnot PGrasset AMillet PKuehnle MRies FHuebner MBecker JCoppola MPieralisi LLocatelli RMaruccia GCampi FDeMarco TSciuto D(2008)Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processorProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403700(1352-1357)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403700
Noori HMehdipour FInoue KMurakami KNarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)Enhancing energy efficiency of processor-based embedded systems through post-fabrication ISA extensionProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1393987(241-246)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1393987
Yi YNousias IMilward MKhawam SArslan TLindsay IGielen G(2006)System-level scheduling on instruction cell based reconfigurable systemsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131584(381-386)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131584
Galanis MDimitroulakos GGoutis C(2006)Partitioning Methodology for Heterogeneous Reconfigurable Functional UnitsThe Journal of Supercomputing10.1007/s11227-006-6743-538:1(17-34)Online publication date: 1-Oct-2006
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Mei BLambrechts AVerkest DMignolet JLauwereins R(2005)Architecture Exploration for a Reconfigurable Architecture TemplateIEEE Design & Test10.1109/MDT.2005.2722:2(90-101)Online publication date: 1-Mar-2005
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Galanis MMilidonis ATheodoridis GSoudris DGoutis C(2005)A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable PlatformsProceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 0410.1109/IPDPS.2005.26Online publication date: 4-Apr-2005
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