research-article

Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor

Authors:

T. DeMarcoAuthors Info & Claims

DATE '08: Proceedings of the conference on Design, automation and test in Europe

Pages 1352 - 1357

https://doi.org/10.1145/1403375.1403700

Published: 10 March 2008 Publication History

Abstract

Reconfigurable architectures and NoC (Network-on-Chip) have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting run-time adaptivity opens a new area of research by considering dynamic reconfiguration. In this paper, we present the architecture and associated development tools of an heterogeneous reconfigurable SoC focusing on the chosen communication infrastructure. The SOC integrates units of various sizes of reconfiguration granularity. The included NoC approach demonstrates the mentioned benefits and scalability for actual and future SoC design.

On a reference CMOS090 implementation the described interconnect system works at the system reference frequency of 200 MHZ sustaining the required run-time bandwidth on a set of reference applications, at a price < 10% in area in power consumption with respect to the overall system.

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Cited By

Motakis AKornaros GCoppola M(2011)Dynamic resource management in modern multicore SoCs by exposing NoC services6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2011.5981503(1-7)Online publication date: Jun-2011
https://doi.org/10.1109/ReCoSoC.2011.5981503
Kim YMahapatra R(2010)Dynamic Context Compression for Low-Power CGRADesign of Low-Power Coarse-Grained Reconfigurable Architectures10.1201/b10471-13(119-140)Online publication date: 9-Dec-2010
https://doi.org/10.1201/b10471-13
Rossi DCampi FSpolzino SPucillo SGuerrieri R(2010)A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable ComputingIEEE Journal of Solid-State Circuits10.1109/JSSC.2010.204814945:8(1615-1626)Online publication date: Aug-2010
https://doi.org/10.1109/JSSC.2010.2048149
Show More Cited By

Index Terms

Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing
2. Hardware
  1. Communication hardware, interfaces and storage

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cover image ACM Conferences

DATE '08: Proceedings of the conference on Design, automation and test in Europe

March 2008

1575 pages

ISBN:9783981080131

DOI:10.1145/1403375

General Chair:
Donatella Sciuto
Politecnico di Milano, Italy

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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The EDA Consortium
EDAA: European Design Automation Association
ECSI
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
IEEE Council on Electronic Design Automation (CEDA)
The Russian Academy of Sciences: The Russian Academy of Sciences

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 March 2008

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DATE '08: Design, Automation and Test in Europe

March 10 - 14, 2008

Munich, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Motakis AKornaros GCoppola M(2011)Dynamic resource management in modern multicore SoCs by exposing NoC services6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2011.5981503(1-7)Online publication date: Jun-2011
https://doi.org/10.1109/ReCoSoC.2011.5981503
Kim YMahapatra R(2010)Dynamic Context Compression for Low-Power CGRADesign of Low-Power Coarse-Grained Reconfigurable Architectures10.1201/b10471-13(119-140)Online publication date: 9-Dec-2010
https://doi.org/10.1201/b10471-13
Rossi DCampi FSpolzino SPucillo SGuerrieri R(2010)A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable ComputingIEEE Journal of Solid-State Circuits10.1109/JSSC.2010.204814945:8(1615-1626)Online publication date: Aug-2010
https://doi.org/10.1109/JSSC.2010.2048149
Ma JWang CWen YChen THu WChen J(2010)Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel ApplicationsProceedings of the 2010 10th IEEE International Conference on Computer and Information Technology10.1109/CIT.2010.462(2768-2775)Online publication date: 29-Jun-2010
https://dl.acm.org/doi/10.1109/CIT.2010.462
Kim YMahapatra R(2009)Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systemsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630123(826-831)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630123
Rosti A(2009)Dissemination of MORPHEUS ResultsDynamic System Reconfiguration in Heterogeneous Platforms10.1007/978-90-481-2427-5_20(251-259)Online publication date: 2009
https://doi.org/10.1007/978-90-481-2427-5_20

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