Browse Theses

The explosive growth in the computational requirements imposed on current day digital systems and the rapid proliferation of portable devices have made low power a critical design issue. Low-power studies published in the literature indicate that large power savings are possible by addressing this problem at the higher--algorithm and architecture--levels of abstraction. In fact, high-level design tools and methodologies are becoming increasingly important due to the integration of tens of millions of transistors on single chips and narrowing time-to-market windows.

This dissertation presents automated techniques and methodologies for power reduction at the algorithm and architecture levels of abstraction. The core contributions include mechanisms for power estimation from a behavioral description, and architecture synthesis techniques for low-power design.

The key contributions in the first part of this work are techniques for algorithm-level power estimation. The estimates are based on information from an architecture model and a specified hardware library, and are hence technology-targeted. Each of the different components of power dissipation on a chip are considered separately, and a combination of analytic and stochastic schemes is proposed. The estimation methods are encapsulated in an exploration framework that allows the user to quickly evaluate several points in the algorithmic design space without synthesizing each one.

The primary contributions in the second part of this work are architecture-synthesis schemes targeting interconnect power reduction. We propose two techniques that are based on exploiting algorithm properties for reducing power. The properties considered are the algorithm's spatial locality, which refers to the existence of tightly connected substructures in it, and its regularity, which refers to the repetition of computational patterns in it. The synthesis approaches suggested exploit these properties to derive a simpler interconnect infrastructure with shorter buses and lower multiplexor and buffer overhead.

The concepts and ideas developed in this thesis have been embodied in a synthesis system called Synergy which allows the user to explore the algorithmic design space and synthesize the design to a low-power architecture in an integrated way.