High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core
Emerging high-level hardware description and synthesis technologies in conjunction with field programmable gate arrays (FPGAs) have significantly lowered the threshold for hardware development. Opportunities exist to integrate these technologies into a ...
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units
A partitioning methodology between the reconfigurable hardware blocks of different granularity, which are embedded in a generic heterogeneous architecture, is presented. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-...
A Parallel Implementation of the Katsevich Algorithm for 3-D CT Image Reconstruction
Yu and Wang [1, 2] implemented the first theoretically exact spiral cone-beam reconstruction algorithm developed by Katsevich [3, 4]. This algorithm requires a high computational cost when the data amount becomes large. Here we study a parallel ...
Addressing a workload characterization study to the design of consistency protocols
Shared Virtual Memory (SVM) provides a low-cost and effective way to implement the shared-memory programming paradigm. SVMs utilize a number of concepts that include consistency models/protocols, sharing patterns, false sharing, and fragmentation ...
The p-sized partitioning algorithm for fast computation of factorials of numbers
Computing products of large numbers has always been a challenging task in the field of computing. One such example would be the factorial function. Several methods have been implemented to compute this function including naive product, recursive product,...
Work-efficient BSR-based parallel algorithms for some fundamental problems in graph theory
This paper presents BSR-parallel algorithms for some problems in fundamental graph theory : transitive closure, connected components, spanning tree, bridges and articulation points of a graph and bipartite graph recognition. There already exist constant ...
