article

Parallel Queue Processor Architecture Based on Produced Order Computation Model

Authors:

Masahiro Sowa,

Ben A. Abderazek,

Tsutomu YoshinagaAuthors Info & Claims

The Journal of Supercomputing, Volume 32, Issue 3

Pages 217 - 229

https://doi.org/10.1007/s11227-005-0160-z

Published: 01 June 2005 Publication History

Abstract

This paper proposes novel produced order parallel queue processor architecture. To store intermediate results, the proposed system uses a first-in-first-out (FIFO) circular queue-registers instead of random access registers. Datum is inserted in the queue-registers in produced order scheme and can be reused. We show that this feature has profound implications in the areas of parallel execution, programs compactness, hardware simplicity and high execution speed.

Our performance evaluations show a significant performance improvement (e.g., 10 to 26% decrease in program size and 6 to 46% decrease in execution time over a range of benchmark programs) when compared with the earlier proposed architecture.

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Cited By

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Canedo AAbderazek BSowa M(2010)Compiling for Reduced Bit-Width Queue ProcessorsJournal of Signal Processing Systems10.1007/s11265-008-0286-359:1(45-55)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s11265-008-0286-3
Fernandes SOliveira BSilva ISaraiva IRibas RPlett C(2009)Using NoC routers as processing elementsProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601927(1-6)Online publication date: 31-Aug-2009
https://dl.acm.org/doi/10.1145/1601896.1601927
Canedo AAbderazek BSowa M(2009)Compiler Support for Code Size Reduction Using a Queue-Based ProcessorTransactions on High-Performance Embedded Architectures and Compilers II10.1007/978-3-642-00904-4_14(269-285)Online publication date: 22-Apr-2009
https://dl.acm.org/doi/10.1007/978-3-642-00904-4_14
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Parallel Queue Processor Architecture Based on Produced Order Computation Model

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cover image The Journal of Supercomputing

The Journal of Supercomputing Volume 32, Issue 3

June 2005

88 pages

ISSN:0920-8542

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Kluwer Academic Publishers

United States

Publication History

Published: 01 June 2005

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Canedo AAbderazek BSowa M(2010)Compiling for Reduced Bit-Width Queue ProcessorsJournal of Signal Processing Systems10.1007/s11265-008-0286-359:1(45-55)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s11265-008-0286-3
Fernandes SOliveira BSilva ISaraiva IRibas RPlett C(2009)Using NoC routers as processing elementsProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601927(1-6)Online publication date: 31-Aug-2009
https://dl.acm.org/doi/10.1145/1601896.1601927
Canedo AAbderazek BSowa M(2009)Compiler Support for Code Size Reduction Using a Queue-Based ProcessorTransactions on High-Performance Embedded Architectures and Compilers II10.1007/978-3-642-00904-4_14(269-285)Online publication date: 22-Apr-2009
https://dl.acm.org/doi/10.1007/978-3-642-00904-4_14
Akanda MAbderazek BSowa M(2008)Dual-execution mode processor architectureThe Journal of Supercomputing10.1007/s11227-007-0151-344:2(103-125)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1007/s11227-007-0151-3
Canedo AAbderazek BSowa M(2007)An efficient code generation algorithm for code size reduction using 1-offset P-code queue computation modelProceedings of the 2007 international conference on Embedded and ubiquitous computing10.5555/1780745.1780768(196-208)Online publication date: 17-Dec-2007
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Abderazek BKawata SSowa M(2006)Design and architecture for an embedded 32-bit QueueCoreJournal of Embedded Computing10.5555/1370998.13710052:2(191-205)Online publication date: 1-Apr-2006
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Abderazek BYoshinaga TSowa M(2006)High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor CoreThe Journal of Supercomputing10.1007/s11227-006-6719-538:1(3-15)Online publication date: 1-Oct-2006
https://dl.acm.org/doi/10.1007/s11227-006-6719-5
Abderazek BKawata SYoshinaga TSowa M(2005)Modular design structure and high-level prototyping for novel embedded processor coreProceedings of the 2005 international conference on Embedded and Ubiquitous Computing10.1007/11596356_36(340-349)Online publication date: 6-Dec-2005
https://dl.acm.org/doi/10.1007/11596356_36

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The QC-2 parallel Queue processor architecture

High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core

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