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Allowing for ILP in an embedded Java processor

Authors:

Ramesh Radhakrishnan,

Deependra Talla,

Lizy Kurian JohnAuthors Info & Claims

ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture

Pages 294 - 305

https://doi.org/10.1145/339647.339702

Published: 01 May 2000 Publication History

Abstract

Java processors are ideal for embedded and network computing applications such as Internet TV's, set-top boxes, smart phones, and other consumer electronics applications. In this paper, we investigate cost-effective microarchitectural techniques to exploit parallelism in Java bytecode streams. Firstly, we propose the use of a fill unit that stores decoded bytecodes into a decoded bytecode cache. This mechanism improves the fetch and decode bandwidth of Java processors by 2 to 3 times. These additional hardware units can also be used to perform optimizations such as instruction folding. This is particularly significant because experiments with the Verilog model of Sun Microsystems pico Java-II core demonstrates that instruction folding lies in the critical path. Moving folding logic from the critical path of the processor to the fill unit allows to improve the clock frequency by 25%. Out-of-order ILP exploitation is not investigated due to the prohibitive cost, but in-order dual-issue with a 64-entry decoded bytecode cache is seen to result in 10% to 14% improvement in execution cycles. Another contribution of the paper is a stack disambiguation technique that allows elimination of false dependencies between different types of stack accesses. Stack disambiguation further exposes parallelism and a dual in-order issue microengine with a 64-entry bytecode cache yields an additional 10% reduction in cycles, leading to an aggregate reduction of 17% to 24% in execution cycles.

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Cited By

Zabel MSpallek RKalibera TVitek J(2010)Application requirements and efficiency of embedded Java bytecode multi-coresProceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems10.1145/1850771.1850777(46-52)Online publication date: 19-Aug-2010
https://dl.acm.org/doi/10.1145/1850771.1850777
Yan LLiang Z(2009)An accelerator design for speedup of Java execution in consumer mobile devicesComputers and Electrical Engineering10.1016/j.compeleceng.2008.11.02135:6(904-919)Online publication date: 1-Nov-2009
https://dl.acm.org/doi/10.1016/j.compeleceng.2008.11.021
Sideris IPekmestzi KEconomakos G(2008)An instruction set extension for java bytecodes translation acceleration2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1109/ICSAMOS.2008.4664854(116-123)Online publication date: Jul-2008
https://doi.org/10.1109/ICSAMOS.2008.4664854
Show More Cited By

Index Terms

Allowing for ILP in an embedded Java processor
1. Computer systems organization
  1. Architectures
    1. Other architectures
2. Hardware
  1. Robustness
    1. Fault tolerance
    2. Hardware reliability

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cover image ACM Conferences

ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture

June 2000

327 pages

ISBN:1581132328

DOI:10.1145/339647

Chairmen:
Alan Berenbaum
Lucent Technologies
,
Joel Emer
Compaq Computer Corp.

ACM SIGARCH Computer Architecture News Volume 28, Issue 2
Special Issue: Proceedings of the 27th annual international symposium on Computer architecture (ISCA '00)
May 2000
325 pages
ISSN:0163-5964
DOI:10.1145/342001
Chairmen:
Alan Berenbaum
Lucent Technologies, Berkeley Heights, NJ
,
Joel Emer
Compaq Computer Corp., Palo Alto, CA
Issue’s Table of Contents

Copyright © 2000 ACM.

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Published: 01 May 2000

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Cited By

Zabel MSpallek RKalibera TVitek J(2010)Application requirements and efficiency of embedded Java bytecode multi-coresProceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems10.1145/1850771.1850777(46-52)Online publication date: 19-Aug-2010
https://dl.acm.org/doi/10.1145/1850771.1850777
Yan LLiang Z(2009)An accelerator design for speedup of Java execution in consumer mobile devicesComputers and Electrical Engineering10.1016/j.compeleceng.2008.11.02135:6(904-919)Online publication date: 1-Nov-2009
https://dl.acm.org/doi/10.1016/j.compeleceng.2008.11.021
Sideris IPekmestzi KEconomakos G(2008)An instruction set extension for java bytecodes translation acceleration2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation10.1109/ICSAMOS.2008.4664854(116-123)Online publication date: Jul-2008
https://doi.org/10.1109/ICSAMOS.2008.4664854
Sideris IPekmestzi KEconomakos G(2008)A predecoding technique for ILP exploitation in Java processorsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2008.01.00854:7(707-728)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1016/j.sysarc.2008.01.008
Wang HYuen C(2006)Exploiting dataflow to extract java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processorProceedings of the 20th international conference on Parallel and distributed processing10.5555/1898953.1898986(52-52)Online publication date: 25-Apr-2006
https://dl.acm.org/doi/10.5555/1898953.1898986
Oi HAlderighi MSalapura VMcKee S(2006)Instruction folding in a hardware-translation based java virtual machineProceedings of the 3rd conference on Computing frontiers10.1145/1128022.1128041(139-146)Online publication date: 3-May-2006
https://dl.acm.org/doi/10.1145/1128022.1128041
Hai-Chen Wang Chung-Kwong Yuen (2006)Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processorProceedings 20th IEEE International Parallel & Distributed Processing Symposium10.1109/IPDPS.2006.1639289(9 pp.)Online publication date: 2006
https://doi.org/10.1109/IPDPS.2006.1639289
Akanda MAbderazek BSowa M(2006)On the design of a dual-execution modes processorProceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking10.1007/11942634_5(37-46)Online publication date: 4-Dec-2006
https://dl.acm.org/doi/10.1007/11942634_5
Sowa MAbderazek BYoshinaga T(2005)Parallel Queue Processor Architecture Based on Produced Order Computation ModelThe Journal of Supercomputing10.1007/s11227-005-0160-z32:3(217-229)Online publication date: 1-Jun-2005
https://dl.acm.org/doi/10.1007/s11227-005-0160-z
Abderazek BArsenji MShigeta SYoshinaga TSowa M(2004)Queue processor architecture for novel queue computing paradigm based on produced order schemeProceedings. Seventh International Conference on High Performance Computing and Grid in Asia Pacific Region, 2004.10.1109/HPCASIA.2004.1324032(169-177)Online publication date: 2004
https://doi.org/10.1109/HPCASIA.2004.1324032
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