research-article

Using NoC routers as processing elements

Authors:

Sílvio Fernandes,

Bruno C. Oliveira,

Ivan Saraiva SilvaAuthors Info & Claims

SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

Article No.: 24, Pages 1 - 6

https://doi.org/10.1145/1601896.1601927

Published: 31 August 2009 Publication History

Abstract

The integration technology has increased at the point where the development of Multi-Core processor architectures is a market reality nowadays. In this scenario, the interconnection network has a critical function when the number of cores increases, becoming impossible to use bus-based solutions. This paper approaches this problem with a new NoC-based architecture and a new computation mode. It proposes the utilization of network-onchip not only as an interconnection network but as well the processing datapath, which has great power of parallelism.

References

[1]

Abderazek, B. A., Yoshinaga, T. and Sowa, M. High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. Kluwer Academic Publishers, 2006; v. 38, pp 3--15.

Digital Library

[2]

Agostini, L. V. Design of integrated architecture to JPEG images compression. Master. Instituto de Informática. Federal University of Rio Grande do Sul, Porto Alegre, 2002, 143 p

[3]

Borkar, V. Platform 2015: Intel processor and platform evolution for the next decade. 2005.

[4]

Canedo, A., Abderazek, B. and Sowa, M. Queue Register File Optimization Algorithm for QueueCore Processor. In: 19th International Symposium on Computer Architecture and High Performance Computing. 2007.

[5]

Omitted due blind review.

[6]

Hord, R. M. Parallel Supercomputing in MIMD Architectures. CRC Press, 1993.

Digital Library

[7]

Intel. iWarp Project, 1988. http://en.wikipedia.org/wiki/IWarp

[8]

Kovac, M. and Ranganathan, N. J. A Fully Pipelined VLSI Architecture for JPEG Image Compression Standard. In: Proceedings of the IEEE. 1995; 247--258.

[9]

Kumar, S., Jantsch, A., Soininen, J.-P., Forsell, M., Millberg, M., Oberg, J., Tiensyrja, K. and Hemani, A. A Network on Chip Architecture and Design Methodology. IEEE Computer Society, 2002.

[10]

Murray, J. D. and Ryper, W. V. Encyclopedia of Graphics File Formats. 2nd; O'Reilly&Associates, Sebastopol, 1996.

Digital Library

[11]

OSCI. SystemC, 2005. http://www.systemc.org

[12]

Pande, P. P., Grecu, C., Ivanov, A. and Saleh, R. Destination network-on-chip. 2005; pp 6--7.

[13]

Preiss, B. R. and Hamacher, V. C. Data Flow on Queue Machines. In: 12th Int. IEEE Symposium on Computer Architecture. 1985; 342--351.

Digital Library

[14]

Omitted due blind review.

[15]

Schmit, H., Levine, B. and Ylvisaker, B. Queue Machines: Hardware Compilation in Hardware. IEEE Computer Society, 2002.

[16]

Omitted due blind review

[17]

Sowa, M., Abderazek, B. A. and Yoshinaga, T. Parallel Queue Processor Architecture Based on Produced Order Computation Model. Kluwer Academic Publishers, 2005; v. 32, pp 217--229.

Digital Library

[18]

U. S. P. a. T. Office. Tran Le Nguyen, H. Network-on-chip dataflow architecture. 11/382,382.2006.

Cited By

Kandemir MRyoo JTang XKarakoy MLee JPetrank E(2021)Compiler support for near data computingProceedings of the 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3437801.3441600(90-104)Online publication date: 17-Feb-2021
https://dl.acm.org/doi/10.1145/3437801.3441600
Shantharama PThyagaturu AReisslein M(2020)Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research StudiesIEEE Access10.1109/ACCESS.2020.30082508(132021-132085)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.3008250
Nunes DFernandes SKreutz M(2019)Optimizing an Architecture with Software Pipelining Strategies2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2019.8920368(299-304)Online publication date: Oct-2019
https://doi.org/10.1109/VLSI-SoC.2019.8920368
Show More Cited By

Index Terms

Using NoC routers as processing elements
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing
    2. Serial architectures
      1. Pipeline computing

Recommendations

A survey of research and practices of Network-on-chip

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the ...
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA
Abstract
The network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips (MPSoCs). The NoC architecture, the routers micro-architecture and links influence the ...
Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks

Future scalability for kilo-core architectures requires solutions beyond the capabilities of protocol and software design. Single-cycle multihop asynchronous repeated traversal (SMART) creates virtual single-cycle paths across the shared network between ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

August 2009

325 pages

ISBN:9781605587059

DOI:10.1145/1601896

General Chair:
Ivan Saraiva
UFRN, Brazil
,
Program Chairs:
Renato Perez Ribas
UFRGS, Brazil
,
Calvin Plett
Carleton University, Canada

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SBC: Brazilian Computer Society
SIGDA: ACM Special Interest Group on Design Automation
SBMICRO: Brazilian Microelectronics Society
IEEE Circuits & Systems Society

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 31 August 2009

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

SBCCI '09

Sponsor:

SBC
SIGDA
SBMICRO

SBCCI '09: 22nd Symposium on Integrated Circuits and System Design

August 31 - September 3, 2009

Natal, Brazil

Acceptance Rates

SBCCI '09 Paper Acceptance Rate 50 of 119 submissions, 42%;

Overall Acceptance Rate 133 of 347 submissions, 38%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

4
Total Citations
View Citations
184
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 30 Jul 2024

Other Metrics

View Author Metrics

Citations

Cited By

Kandemir MRyoo JTang XKarakoy MLee JPetrank E(2021)Compiler support for near data computingProceedings of the 26th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/3437801.3441600(90-104)Online publication date: 17-Feb-2021
https://dl.acm.org/doi/10.1145/3437801.3441600
Shantharama PThyagaturu AReisslein M(2020)Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research StudiesIEEE Access10.1109/ACCESS.2020.30082508(132021-132085)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.3008250
Nunes DFernandes SKreutz M(2019)Optimizing an Architecture with Software Pipelining Strategies2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2019.8920368(299-304)Online publication date: Oct-2019
https://doi.org/10.1109/VLSI-SoC.2019.8920368
Soares TSilva IFernandes Sde Lima RCunha APlett Cde Oliveira W(2015)IPNoSys IIProceedings of the 28th Symposium on Integrated Circuits and Systems Design10.1145/2800986.2801012(1-7)Online publication date: 31-Aug-2015
https://dl.acm.org/doi/10.1145/2800986.2801012

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents