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- research-articleAugust 2009
BRICK: a multi-context expression grained reconfigurable architecture
SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the DunesAugust 2009, Article No.: 36, Pages 1–6https://doi.org/10.1145/1601896.1601942In this work, we explore a new family of coarse grain reconfigurable architecture called BRICK, which is capable of mapping complete expressions and pipelines into one processing element with Multiple-Input, Multiple-Output characteristics while ...
- research-articleAugust 2009
ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networks
SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the DunesAugust 2009, Article No.: 35, Pages 1–6https://doi.org/10.1145/1601896.1601941This paper presents a new processor architecture for high performance computing of fixed-point feedforward multi layered perceptron neural networks. The number of layers, the number of neurons in each layer, the weight values and the activation function ...
- research-articleAugust 2009
Using NoC routers as processing elements
SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the DunesAugust 2009, Article No.: 24, Pages 1–6https://doi.org/10.1145/1601896.1601927The integration technology has increased at the point where the development of Multi-Core processor architectures is a market reality nowadays. In this scenario, the interconnection network has a critical function when the number of cores increases, ...
