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Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks

Published: 01 October 2013 Publication History

Abstract

Future scalability for kilo-core architectures requires solutions beyond the capabilities of protocol and software design. Single-cycle multihop asynchronous repeated traversal (SMART) creates virtual single-cycle paths across the shared network between cores, potentially offering significant reductions in runtime latency and energy expenditure.

Cited By

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  • (2017)Task Mapping on SMART NoCProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062323(1-6)Online publication date: 18-Jun-2017
  • (2016)Making the internet-of-things a realityProceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.1145/2968456.2973272(1-10)Online publication date: 1-Oct-2016
  • (2016)High-Performance and Energy-Efficient Network-on-Chip Architectures for Graph AnalyticsACM Transactions on Embedded Computing Systems10.1145/296102715:4(1-26)Online publication date: 1-Sep-2016
  • Show More Cited By

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Published In

cover image Computer
Computer  Volume 46, Issue 10
October 2013
105 pages

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 October 2013

Author Tags

  1. NoC
  2. SoC
  3. cache coherence traffic
  4. efficient network design
  5. interconnection network
  6. multicore architecture
  7. network-on-chip
  8. on-chip latency
  9. parallel computer architecture
  10. private L2
  11. scalability
  12. scalable networks
  13. shared L2
  14. system-on-chip

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Cited By

View all
  • (2017)Task Mapping on SMART NoCProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062323(1-6)Online publication date: 18-Jun-2017
  • (2016)Making the internet-of-things a realityProceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.1145/2968456.2973272(1-10)Online publication date: 1-Oct-2016
  • (2016)High-Performance and Energy-Efficient Network-on-Chip Architectures for Graph AnalyticsACM Transactions on Embedded Computing Systems10.1145/296102715:4(1-26)Online publication date: 1-Sep-2016
  • (2016)Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request NetworkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.253828424:10(3013-3026)Online publication date: 1-Oct-2016
  • (2016)Network-on-Chip-Enabled Multicore Platforms for Parallel Model Predictive ControlIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.252812124:9(2837-2850)Online publication date: 23-Aug-2016
  • (2015)Core vs. uncoreProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2747916(1-6)Online publication date: 7-Jun-2015
  • (2014)NoC-SprintingProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593165(1-6)Online publication date: 1-Jun-2014

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