article

Design and architecture for an embedded 32-bit QueueCore

Authors:

Ben A. Abderazek,

Masahiro SowaAuthors Info & Claims

Journal of Embedded Computing, Volume 2, Issue 2

Pages 191 - 205

Published: 01 April 2006 Publication History

Abstract

Queue based instruction set architecture processor offers an attractive option in the design of embedded systems by providing high performance for a specific application. This work describes the design results and methodology of a queue processor core, named QueueCore, as a starting point for application-specific processor (ASP) design. By using simple and common base queue instruction set, the design space exploration is focused on the application-specific aspects of performance.

In any new architecture, verification, which usually requires complicated and lengthy software simulation of an emulated model, is an important aspect. We show how cooperative hardware emulation, based on programmable logic, can be integrated into a co-design flow to evaluate the performance of the novel QueueCore processor and to verify the functional correctness of a specific benchmark on the system core.

To avoid duplication of the design effort, different target implementations are derived from a common source. We present the evaluation results of the QueueCore for three different platforms.

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Cited By

Abderazek BMasuda MCanedo AKuroda K(2011)Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architectureThe Journal of Supercomputing10.1007/s11227-010-0409-z57:3(314-338)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1007/s11227-010-0409-z
Canedo AAbderazek BSowa M(2010)Compiling for Reduced Bit-Width Queue ProcessorsJournal of Signal Processing Systems10.1007/s11265-008-0286-359:1(45-55)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s11265-008-0286-3
Canedo AAbderazek BSowa M(2007)An efficient code generation algorithm for code size reduction using 1-offset P-code queue computation modelProceedings of the 2007 international conference on Embedded and ubiquitous computing10.5555/1780745.1780768(196-208)Online publication date: 17-Dec-2007
https://dl.acm.org/doi/10.5555/1780745.1780768
Show More Cited By

Index Terms

Design and architecture for an embedded 32-bit QueueCore
1. Hardware
  1. Integrated circuits
    1. Logic circuits
  2. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

Index terms have been assigned to the content through auto-classification.

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Information

Published In

cover image Journal of Embedded Computing

Journal of Embedded Computing Volume 2, Issue 2

Issues in embedded single-chip multicore architectures

April 2006

126 pages

ISSN:1740-4460

Issue’s Table of Contents

Publisher

IOS Press

Netherlands

Publication History

Published: 01 April 2006

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Cited By

Abderazek BMasuda MCanedo AKuroda K(2011)Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architectureThe Journal of Supercomputing10.1007/s11227-010-0409-z57:3(314-338)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1007/s11227-010-0409-z
Canedo AAbderazek BSowa M(2010)Compiling for Reduced Bit-Width Queue ProcessorsJournal of Signal Processing Systems10.1007/s11265-008-0286-359:1(45-55)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1007/s11265-008-0286-3
Canedo AAbderazek BSowa M(2007)An efficient code generation algorithm for code size reduction using 1-offset P-code queue computation modelProceedings of the 2007 international conference on Embedded and ubiquitous computing10.5555/1780745.1780768(196-208)Online publication date: 17-Dec-2007
https://dl.acm.org/doi/10.5555/1780745.1780768
Canedo AAbderazek BSowa M(2007)An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation ModelEmbedded and Ubiquitous Computing10.1007/978-3-540-77092-3_18(196-208)Online publication date: 17-Dec-2007
https://dl.acm.org/doi/10.1007/978-3-540-77092-3_18

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