A PGAS execution model for efficient stencil computation on many-core processors
Pages 305 - 314
Abstract
A efficient PGAS execution model on many-core processor for stencil computation is proposed and implemented. We use XcalableMP as a base language and we modify its runtime well fit in many-core processors. The runtime uses processes for parallel execution and global arrays of the stencil codes are broken into blocked sub-arrays placed on shared memory. Using two stencil codes, Laplace and Himeno, we evaluated its performance. In the evaluation, we show (1) Blocking improves locality of memory access during computation therefore improves total CPU execution time. (2) Direct data access using shared memory can relieve communication burden of sub-array halo exchanges.
References
[1]
M. Ikei and M. Sato, "A study of pgas language xcalablemp runtime for many-core processor cluster," IPSJ(HPC), vol. 2013-HPC-140, no. 30, pp. 1--8, 2013, (in Japanese).
[2]
XcalableMP Specification Working Group, "Xcalablemp specification version 1.1," 11 2012, http://www.xcalablemp.org/spec/xmp-spec-1.1.pdf.
[3]
K. Raman, "Optimizing memory bandwidth on stream triad," 2 2013, http://software.intel.com/en-us/articles/optimizing-memory-bandwidth-on-stream-triad.
[4]
Riken, "Himeno benchmark," http://accc.riken.jp/2444.htm.
[5]
A. Heinecke, K. Vaidyanathan, M. Smelyanskiy, A. Kobotov, R. Dubtsov, G. Henry, A. G. Shet, G. Chrysos, and P. Dube, "Design and Implementation of the Linpack Benchmark for Single and Multi-Node Systems Based on Inte Xeon Phi Coprocessor," IPDPS, 2013.
[6]
A. H. Qingyu Meng, J. Schmidt, and M. Berzins, "Preliminary Experiences with the Uintah Framework on Intel Xeon Phi and Stampedei," XSEDE13, July 2013.
[7]
D. Schmid, T. Cramer, SandraWienke, C. Terboven, and M. S. Muller, "Assessing the Performance of OpenMP Programs on the Intel Xeon Phi," Euro-Par 2013, 2013.
[8]
Y. Li, Y. Che, and Z. Wang, "Performance Evaluation and Scalability Analysis of NPB-MZ on Intel Xeon Phi Coprocessor," NCCET 2013, 2013.
[9]
G. Misra, A. D. Nisha Kurkure, M. Valmiki, and A. G. Shweta Das, "Evaluation of Rodinia Codes on Intel Xeon Phi," ISMS, 2013.
[10]
Y. You, H. F. amd Xiaomeng Huang, G. Song, L. Gan, W. Yu, and G. Yangr, "Accelerating the 3D Elastic Wave Forward Modeling on GPU and MIC," IPDPSW, 2013.
[11]
G.Crimia, F.Mantovanib, M.Pivantid, S.F.Schifanoe, and R.Tripiccionec, "Early experience on porting and running a Lattice Boltzmann code on the Xeon-Phi co-processor," ICCS, 2013.
[12]
B. J. N.Wylie and W. Frings, "Scalasca support for MPI+OpenMP parallel applications on large-scale HPC systems based on Intel Xeon Phi," XSEDE13, July 2013.
[13]
R. Rahman, Algorithm and Data Structures for Xeon Phi. A Press, 2013.
[14]
M. McCool, J. Reinders, and A. Robison, Structured Parallel Programming: Patterns for Efficient Computation. Morgan Kaufmann, 2012.
[15]
S. Ramos and T. Hoefler, "Modeling Communication in Cache-Coherent SMP Systems - A Case-Study with Xeon Phi," HPDC 13, June 2013.
- A PGAS execution model for efficient stencil computation on many-core processors
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Published: 26 May 2014
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CCGrid '14: 2014 IEEE International Symposium on Cluster Computing and the Grid
May 26 - 29, 2014
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