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View all- Harcourt E(2019)Policies of System Level Pipeline ModelingElectronic Notes in Theoretical Computer Science (ENTCS)10.1016/j.entcs.2009.05.003238:2(13-23)Online publication date: 5-Jan-2019
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
Pages 786 - 791
Abstract
Detailed modeling of processors and high performance cycle-accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we propose the Reduced Colored Petri Net (RCPN) model that has two advantages: first, it offers a very simple and intuitive way of modeling pipelined processors; second, it can generate high performance cycle-accurate simulators. RCPN benefits from all the useful features of Colored Petri Nets without suffering from their exponential growth in complexity. RCPN processor models are very intuitive since they are a mirror image of the processor pipeline block diagram. Furthermore, in our experiments on the generated cycle-accurate simulators for XScale and StrongArm processor models, we achieved an order of magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator.
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Index Terms
- Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
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March 2005
630 pages
ISBN:0769522882
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IEEE Computer Society
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Published: 07 March 2005
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View all- Harcourt E(2019)Policies of System Level Pipeline ModelingElectronic Notes in Theoretical Computer Science (ENTCS)10.1016/j.entcs.2009.05.003238:2(13-23)Online publication date: 5-Jan-2019
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