Cited By
View all- Balakrishnan KTouba N(2006)Improving linear test data compressionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88641714:11(1227-1237)Online publication date: 1-Nov-2006
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Pages 1130 - 1135
Abstract
A methodology for designing a reconfigurable linear decompressor is presented. A symbolic Gaussian elimination method to solve a constrained Boolean matrix is proposed and utilized for designing the reconfigurable network. The proposed scheme can be implemented in conjunction with any decompressor that has a combinational linear network. Using the given linear decompressor as a starting point, the proposed method improves the compression further. A nice feature of the proposed method is that it can be implemented with very little hardware overhead. Experimental results indicate that significant improvements can be achieved.
References
[1]
{1} I. Bayraktaroglu and A. Orailoglu. Test volume and application time reduction through scan chain concealment. In Proc. of Design Automation Conference, pages 151-155, 2001.
[2]
{2} I. Bayraktaroglu and A. Orailoglu. Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression. In Proc. of VLSI Test Symposium, pages 113-118, 2003.
[3]
{3} F. Brglez, D. Bryan, and K. Kozminski. Combinational profiles of sequential benchmark circuits. In Proc. of International Symposium on Circuits and Systems, page 1929-1934, 1989.
[4]
{4} M. Chandramouli. How to implement deterministic logic built-in self-test (BIST). Complier: A Monthly Magazine for Technologists Worldwide, Jan. 2003.
[5]
{5} C. Cullen. Linear Algebra with Applications. Addison-Wesley, 1997.
[6]
{6} I. Hamzaoglu and J. Patel. Reducing test application time for full scan embedded cores. In Proc. of Int. Symposium on Fault Tolerant Computing, pages 260-267, 1999.
[7]
{7} F. Hsu, K. M. Butler, and J. H. Patel. A case study on the implementation of the illinois scan architecture. In Proc. of International Test Conference, pages 538-547, 2001.
[8]
{8} A. Jas, B. Pouya, and N. Touba. Virtual scan chains: A means for reducing scan length in cores. In Proc. of VLSI Test Symposium, pages 73-78, 2000.
[9]
{9} A. Khoche and J. Rivoir. I/O bandwidth bottleneck for test: Is it real? In Proc. of International Workshop on Test Resource Partitioning, 2000.
[10]
{10} B. Konemann. LFSR-coded test patterns for scan designs. In Proc. of European Test Conference, pages 237-242, 1991.
[11]
{11} B. Konemann. A smartBIST variant with guaranteed encoding. In Proc. of Asian Test Symposium, pages 325-330, 2001.
[12]
{12} C. Krishna and N. Touba. Reducing test data volume using LFSR reseeding with seed compression. In Proc. of International Test Conference, pages 321-330, 2001.
[13]
{13} C. Krishna and N. Touba. Adjustable width linear combinational scan vector decompression. In Proc. of International Conference on Computer-Aided Design (ICCAD), pages 863-866, 2003.
[14]
{14} C. Krishna and N. Touba. 3-stage variable length continuous-flow scan vector decompression scheme. In Proc. of VLSI Test Symposium, pages 79-86, 2004.
[15]
{15} L. Li and K. Chakrabarty. Deterministic BIST based on a reconfigurable interconnection network. In Proc. of International Test Conference, pages 460-469, 2003.
[16]
{16} S. Mitra and K. Kim. Xmax: X-tolerant architectures for maximal test compression. In Proc. of International Conference on Computer Design, pages 326-330, 2003.
[17]
{17} J. Rajski and et al. Embedded deterministic test for low cost manufacturing test. In Proc. of Int. Test Conference, pages 301-310, 2002.
[18]
{18} W. Rao, I. Bayraktaroglu, and A. Orailoglu. Test application time and volume compression through seed overlapping. In Proc. of Design Automation Conference, pages 732-737, 2003.
[19]
{19} H. Tang, S. Reddy, and I. Pomeranz. On reducing test data volume and test application time for multiple scan chain designs. In Proc. of International Test Conference, pages 1079-1088, 2003.
Index Terms
- Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Recommendations
Using Statistical Transformations to Improve Compression for Linear Decompressors
DFT '05: Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI SystemsLinear decompressors are the dominant methodology used in commercial test data compression tools. However, they are generally not able to exploit correlations in the test data, and thus the amount of compression that can be achieved with a linear ...
32-bit floating-point FPGA gaussian elimination
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arraysThe well-known Gaussian elimination (with partial pivoting) is a widely-used algorithm, one of traditional methods for solving dense linear systems of equations (LSEs). This paper presents a hardware-optimized variant of Gaussian elimination and its 32-...
A New Paradigm for Synthesis of Linear Decompressors
DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017For more than two decades, the key objective for synthesis of linear decompressors has been maximizing encoding efficiency. For combinational decompressors, encoding satisfiability is dynamically checked for each specified care bit. By contrast, for ...
Comments
Information & Contributors
Information
Published In
March 2005
630 pages
ISBN:0769522882
Sponsors
Publisher
IEEE Computer Society
United States
Publication History
Published: 07 March 2005
Check for updates
Qualifiers
- Article
Conference
DATE05
Sponsor:
Acceptance Rates
Overall Acceptance Rate 518 of 1,794 submissions, 29%
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations1Total Citations
- 9Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 06 Oct 2024
Other Metrics
Citations
Cited By
View all- Balakrishnan KTouba N(2006)Improving linear test data compressionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88641714:11(1227-1237)Online publication date: 1-Nov-2006
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in