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Adjustable Width Linear Combinational Scan Vector Decompression

Published: 09 November 2003 Publication History

Abstract

A new scheme for combinational linear expansion isproposed for decompression of scan vectors. It has thecapability to adjust the width of the linear expansion each clockcycle. This eliminates the requirement that every scan bit-slicebe in the output space of the linear decompressor. Depending onhow specified the current bit-slice is, the decompressor may loadall scan chains or may load only a subset of the scan chains.This provides the nice feature that any scan vector can begenerated using the proposed scheme regardless of the numberor distribution of the specified bits. Thus, the proposed schemeallows the use of any ATPG procedure without any constraints.Moreover, it allows greater compression to be achieved thanfixed width expansion techniques since the ratio of the number ofscan chains to the number of tester channels can be scaled muchlarger. A procedure for designing and optimizing the adjustablewidth decompression hardware and obtaining the compresseddata is described. Experimental data indicates that the proposedscheme is simple yet very effective.

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cover image ACM Conferences
ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
November 2003
899 pages
ISBN:1581137621

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IEEE Computer Society

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Published: 09 November 2003

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ICCAD '03 Paper Acceptance Rate 129 of 490 submissions, 26%;
Overall Acceptance Rate 457 of 1,762 submissions, 26%

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  • (2010)Correlation-based rectangular encodingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202588218:10(1483-1492)Online publication date: 1-Oct-2010
  • (2009)Deviation-based LFSR reseeding for test-data compressionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200916628:2(259-271)Online publication date: 1-Feb-2009
  • (2008)State skip LFSRsProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403488(474-479)Online publication date: 10-Mar-2008
  • (2008)Multilevel-Huffman test-data compression for IP cores with multiple scan chainsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200044816:7(926-931)Online publication date: 1-Jul-2008
  • (2006)Improving linear test data compressionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88641714:11(1227-1237)Online publication date: 1-Nov-2006
  • (2006)Survey of Test Vector Compression TechniquesIEEE Design & Test10.1109/MDT.2006.10523:4(294-303)Online publication date: 1-Jul-2006
  • (2005)Reconfigurable Linear Decompressors Using Symbolic Gaussian EliminationProceedings of the conference on Design, Automation and Test in Europe - Volume 210.1109/DATE.2005.255(1130-1135)Online publication date: 7-Mar-2005
  • (2004)Frugal linear network-based test decompression for drastic test cost reductionsProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382670(721-725)Online publication date: 7-Nov-2004

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