research-article

Survey of Test Vector Compression Techniques

Author:

Nur A. ToubaAuthors Info & Claims

IEEE Design & Test, Volume 23, Issue 4

Pages 294 - 303

https://doi.org/10.1109/MDT.2006.105

Published: 01 July 2006 Publication History

Abstract

Test data compression consists of test vector compression on the input side and response compaction on the output side. Test vector compression has been an active area of research, yielding a wide variety of techniques. This article summarizes and categorizes these techniques, explaining how they relate to one another. The goal is to provide a framework for understanding the theory and research in this area.

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C.V. Krishna and N.A. Touba, "Adjustable Width Linear Combinational Scan Vector Decompression," Proc. Int'l Conf. Computer-Aided Design (ICCAD 03), IEEE CS Press, pp. 863–866.

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Cited By

Pomeranz I(2024)Dynamic Test Compaction of a Compressed Test Set Shared Among Logic BlocksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.330735243:1(394-402)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3307352
Chao ZZhang XHuang JYe JCai SLi HLi XKim T(2024)A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT SolverProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473833(503-508)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473833
Pomeranz I(2023)Dummy Faulty Units for Reduced Fail Data Volume From Logic FaultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.330438031:11(1754-1762)Online publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3304380
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Index Terms

Survey of Test Vector Compression Techniques
1. General and reference
  1. Document types
    1. Surveys and overviews
2. Hardware
  1. Hardware test
  2. Robustness

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Published In

cover image IEEE Design & Test

IEEE Design & Test Volume 23, Issue 4

July 2006

64 pages

ISSN:0740-7475

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Copyright © 2006.

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 July 2006

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Test Vector Compression

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Cited By

Pomeranz I(2024)Dynamic Test Compaction of a Compressed Test Set Shared Among Logic BlocksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.330735243:1(394-402)Online publication date: 1-Jan-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3307352
Chao ZZhang XHuang JYe JCai SLi HLi XKim T(2024)A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT SolverProceedings of the 29th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC58780.2024.10473833(503-508)Online publication date: 22-Jan-2024
https://dl.acm.org/doi/10.1109/ASP-DAC58780.2024.10473833
Pomeranz I(2023)Dummy Faulty Units for Reduced Fail Data Volume From Logic FaultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.330438031:11(1754-1762)Online publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3304380
Pomeranz I(2023)Sharing of Compressed Tests Among Logic BlocksIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.324480431:4(421-430)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3244804
Eggersglüß SMilewski SRajski JTyszer J(2023)A New Static Compaction of Deterministic Test SetsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.324024631:4(411-420)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3240246
Angione FAppello DBernardi PBertani CGallo GLittardi SPollaccia GRuggeri WReorda MTancorre VUgioli R(2023)A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical StressIEEE Transactions on Computers10.1109/TC.2022.319999472:5(1447-1459)Online publication date: 1-May-2023
https://dl.acm.org/doi/10.1109/TC.2022.3199994
Addepalli HPomeranz ISavidis ISasan AThapliyal HDeMara R(2022)Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied TestsProceedings of the Great Lakes Symposium on VLSI 202210.1145/3526241.3530359(345-349)Online publication date: 6-Jun-2022
https://dl.acm.org/doi/10.1145/3526241.3530359
Tseng W(2021)A Cascaded Multicasting Architecture for Test Data CompressionJournal of Electronic Testing: Theory and Applications10.1007/s10836-021-05937-137:2(205-214)Online publication date: 1-Apr-2021
https://dl.acm.org/doi/10.1007/s10836-021-05937-1
Lee DKwon SKim BJeon YPark BYun JLarochelle HRanzato MHadsell RBalcan MLin H(2020)FleXORProceedings of the 34th International Conference on Neural Information Processing Systems10.5555/3495724.3495835(1311-1321)Online publication date: 6-Dec-2020
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Liu YMukherjee NRajski JReddy STyszer J(2020)Deterministic Stellar BIST for Automotive ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.292535339:8(1699-1710)Online publication date: 1-Aug-2020
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