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DATA COMPRESSION FOR MULTIPLE SCAN CHAINS USING DICTIONARIES WITH CORRECTIONS

Published: 26 October 2004 Publication History

Abstract

Reducing test application time and test data volume are major challenges in SoC design. In the case of IP cores, where no structural information is available, a common strategy is to compress the test data TD provided by the core vendor into an encoded format TE. Only the smaller set TE is stored on the ATE, and during test the original test data TD are regenerated by an on-chip decompressor. However, most of the encoding schemes suffer from two major drawbacks: Firstly, the irregularity of the encoded test data requires a complex test control including a handshake between the ATE and the system under test. Secondly, compression and decompression is very efficient for circuits with a single scan chain, however the extension to multiple scan chains requires either a separate decompressor for each chain or a serialization of the test data. So far, only a few approaches have been proposed trying to overcome these problems. Instead of dealing with the test vectors these approaches work with the slices to be fed into the scan chains, but they still allow a considerable degree of irregularity in the test application process. In this paper we propose a new dictionary based compression scheme which allows a fully regular test application while keeping the storage requirements low. Due to the regularity of the scheme the advantages of a multiple-scan architecture are preserved, and very low test times can be achieved.

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    Published In

    cover image Guide Proceedings
    ITC '04: Proceedings of the International Test Conference on International Test Conference
    October 2004
    1394 pages
    ISBN:0780385810

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 26 October 2004

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    • (2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
    • (2011)Compression-aware capture power reduction for at-speed testingProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950968(806-811)Online publication date: 25-Jan-2011
    • (2011)Capture-power-aware test data compression using selective encodingIntegration, the VLSI Journal10.1016/j.vlsi.2011.01.00544:3(205-216)Online publication date: 1-Jun-2011
    • (2010)Reducing the storage requirements of a test sequence by using a background vectorProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871224(1237-1242)Online publication date: 8-Mar-2010
    • (2008)GECOMProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356943(577-582)Online publication date: 21-Jan-2008
    • (2007)A selective pattern-compression scheme for power and test-data reductionProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326180(520-525)Online publication date: 5-Nov-2007
    • (2007)CacheCompressProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326178(509-512)Online publication date: 5-Nov-2007
    • (2006)Concurrent core test for SOC using shared test set and scan chain disableProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131770(1045-1050)Online publication date: 6-Mar-2006
    • (2006)FCSCANProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118454(653-658)Online publication date: 24-Jan-2006
    • (2006)Survey of Test Vector Compression TechniquesIEEE Design & Test10.1109/MDT.2006.10523:4(294-303)Online publication date: 1-Jul-2006
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