Article

VirtualScan: A New Compressed Scan Technology for Test Cost Reduction

Authors:

Laung-Terng Wang,

Khader S. Abdel-Hafez,

Sen-Wei TsaiAuthors Info & Claims

ITC '04: Proceedings of the International Test Conference on International Test Conference

Pages 916 - 925

Published: 26 October 2004 Publication History

Publisher Site

Abstract

This paper describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction.

Cited By

View all

Shantagiri PKapur R(2018)Handling Unknown with Blend of Scan and Scan CompressionJournal of Electronic Testing: Theory and Applications10.1007/s10836-018-5717-x34:2(135-146)Online publication date: 1-Apr-2018
https://dl.acm.org/doi/10.1007/s10836-018-5717-x
Vohra HSingh A(2016)Optimal Selective Count Compatible Runlength Encoding for SOC Test Data CompressionJournal of Electronic Testing: Theory and Applications10.1007/s10836-016-5617-x32:6(735-747)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10836-016-5617-x
Da Rolt JDas ADi Natale GFlottes MRouzeyre BVerbauwhede I(2012)A new scan attack on RSA in presence of industrial countermeasuresProceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design10.1007/978-3-642-29912-4_8(89-104)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1007/978-3-642-29912-4_8
Show More Cited By

Index Terms

VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
1. Hardware
  1. Hardware validation
  2. Robustness

Index terms have been assigned to the content through auto-classification.

Recommendations

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

This article describes a test compression technology, called VirtualScan, which achieves scan test cost reduction by inserting a small combinational broadcaster and compactor into the original circuit under test (CUT). In addition, one-pass ATPG takes ...
A Reduction of Grid-Bag Layout to Auckland Layout
ASWEC '10: Proceedings of the 2010 21st Australian Software Engineering Conference

Many major programming platforms support layout managers in Grid-bag style, where GUI elements can be placed on a rectangular grid. In Grid-bag layout mangers, cells of the underlying grid can be merged in order to create more complex layouts. In this ...
On reducing test application time for scan circuits using limited scan operations and transfer sequences

The test application time of a scan circuit is a significant factor in the overall test cost of the circuit. Therefore, reducing the test application time is an important problem. The test application time of a test set for a scan circuit is determined ...

Comments

Information & Contributors

Information

Published In

ITC '04: Proceedings of the International Test Conference on International Test Conference

October 2004

1394 pages

ISBN:0780385810

Publisher

IEEE Computer Society

United States

Publication History

Published: 26 October 2004

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

12
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 06 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Shantagiri PKapur R(2018)Handling Unknown with Blend of Scan and Scan CompressionJournal of Electronic Testing: Theory and Applications10.1007/s10836-018-5717-x34:2(135-146)Online publication date: 1-Apr-2018
https://dl.acm.org/doi/10.1007/s10836-018-5717-x
Vohra HSingh A(2016)Optimal Selective Count Compatible Runlength Encoding for SOC Test Data CompressionJournal of Electronic Testing: Theory and Applications10.1007/s10836-016-5617-x32:6(735-747)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10836-016-5617-x
Da Rolt JDas ADi Natale GFlottes MRouzeyre BVerbauwhede I(2012)A new scan attack on RSA in presence of industrial countermeasuresProceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design10.1007/978-3-642-29912-4_8(89-104)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1007/978-3-642-29912-4_8
Lee JTouba N(2010)Correlation-based rectangular encodingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202588218:10(1483-1492)Online publication date: 1-Oct-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2025882
Miyase KYamato YNoda KIto HHatayama KAikyo TWen XKajihara SRoychowdhury J(2009)A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environmentProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687420(97-104)Online publication date: 2-Nov-2009
https://dl.acm.org/doi/10.1145/1687399.1687420
Shi YTogawa NYanagisawa MOhtsuki TKyung CChoi KHa S(2008)GECOMProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356943(577-582)Online publication date: 21-Jan-2008
https://dl.acm.org/doi/10.5555/1356802.1356943
Lin CChen HGielen G(2007)A selective pattern-compression scheme for power and test-data reductionProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326180(520-525)Online publication date: 5-Nov-2007
https://dl.acm.org/doi/10.5555/1326073.1326180
Zeng GIto HGielen G(2006)Concurrent core test for SOC using shared test set and scan chain disableProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131770(1045-1050)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131770
Shi YTogawa NKimura SYanagisawa MOhtsuki THirose F(2006)FCSCANProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118454(653-658)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118454
Touba N(2006)Survey of Test Vector Compression TechniquesIEEE Design & Test10.1109/MDT.2006.10523:4(294-303)Online publication date: 1-Jul-2006
https://dl.acm.org/doi/10.1109/MDT.2006.105
Show More Cited By

Abstract

Cited By

Index Terms

Recommendations

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

A Reduction of Grid-Bag Layout to Auckland Layout

On reducing test application time for scan circuits using limited scan operations and transfer sequences

Comments

Information

Published In

Publisher

Publication History

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations