research-article

Deterministic Stellar BIST for Automotive ICs

Authors:

Nilanjan Mukherjee,

Sudhakar M. Reddy,

Jerzy TyszerAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 39, Issue 8

Pages 1699 - 1710

https://doi.org/10.1109/TCAD.2019.2925353

Published: 01 August 2020 Publication History

Abstract

As the automotive industry enters a period of rapid evolution changing the way cars are designed and produced, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing around 120 MCUs. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. This paper presents Stellar BIST—a next generation compression scheme for in-system automotive test. The proposed solution can work with any sequential test compression. It builds on a finding that certain clusters of test vectors are capable of detecting many random-resistant faults, where a cluster consists of a parent (base) pattern and its transformed derivatives. Stellar BIST involves generating vectors based on simultaneous and multiple complements of scan slices of encodable parent patterns. The multiple complements are also skewed between successive patterns to diversify the resultant tests. The new scheme elevates compression to values unachievable through conventional reseeding-based solutions and provides significant tradeoffs between storage requirements and test application time, critical for in-system automotive applications. The experimental results obtained for industrial designs and different fault models illustrate feasibility of the proposed test scheme and are reported herein.

References

[1]

C. Aceroet al., “Embedded deterministic test points,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 10, pp. 2949–2961, Oct. 2017.

Digital Library

[2]

A. A. Al-Yamani, S. Mitra, and E. J. McCluskey, “BIST reseeding with very few seeds,” in Proc. VTS, 2003, pp. 69–76.

[3]

C. Barnhartet al., “Extending OPMISR beyond $10\times$ scan test efficiency,” IEEE Design Test, vol. 19, no. 5, pp. 65–73, Sep. 2002.

Digital Library

[4]

M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Boston, MA, USA: Kluwer, 2000.

Digital Library

[5]

K. Chakrabarty, B. T. Murray, and V. Iyengar, “Built-in test pattern generation for high-performance circuits using twisted-ring counters,” in Proc. VTS, 1999, pp. 22–27.

[6]

D. Czysz, G. Mrugalski, N. Mukherjee, J. Rajski, and J. Tyszer, “Highly X-tolerant selective compaction of test responses,” in Proc. VTS, 2009, pp. 245–250.

[7]

D. Czysz, G. Mrugalski, N. Mukherjee, J. Rajski, P. Szczerbicki, and J. Tyszer, “Deterministic clustering of incompatible test cubes for higher power-aware EDT compression,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 30, no. 8, pp. 1225–1238, Aug. 2011.

Digital Library

[8]

D. Das and N. A. Touba, “Reducing test data volume using external/LBIST hybrid test patterns,” in Proc. ITC, 2000, pp. 115–122.

[9]

R. Dorsch and H.-J. Wunderlich, “Tailoring ATPG for embedded testing,” in Proc. ITC, 2001, pp. 530–537.

[10]

X. Fan, S. M. Reddy, S. Wang, S. Kajihara, and Y. Sato, “Genetic algorithm based approach for segmented testing,” in Proc. Int. Conf. Depend. Syst. Netw. Workshops, 2011, pp. 85–90.

[11]

M. Filipek, G. Mrugalski, N. Mukherjee, J. Rajski, and J. Tyszer, “New test compression scheme based-on low power BIST,” in Proc. ETS, 2013, pp. 131–136.

[12]

V. Gherman, H.-J. Wunderlich, J. Schloeffel, and M. Garbers, “Deterministic logic BIST for transition fault testing,” in Proc. ETS, 2006, pp. 123–130.

[13]

V. Gherman, H.-J. Wunderlich, H. P. E. Vranken, F. Hapke, M. Wittke, and M. Garbers, “Efficient pattern mapping for deterministic logic BIST,” in Proc. ITC, 2004, pp. 48–56.

[14]

P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, and H.-J. Wunderlich, “High defect coverage with low-power test sequences in a BIST environment,” IEEE Design Test Comput., vol. 19, no. 5, pp. 44–52, Sep./Oct. 2002.

Digital Library

[15]

A.-W. Hakmi, S. Holst, H.-J. Wunderlich, J. Schloffel, F. Hapke, and A. Glowatz, “Restrict encoding for mixed-mode BIST,” in Proc. VTS, 2009, pp. 179–184.

[16]

A.-W. Hakmiet al., “Programmable deterministic built-in self-test,” in Proc. ITC, 2007, paper 18.1.

[17]

F. Hapkeet al., “Cell-aware test,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 33, no. 9, pp. 1396–1409, Sep. 2014.

[18]

S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A mixed mode BIST scheme based on reseeding of folding counters,” in Proc. ITC, 2000, pp. 778–784.

[19]

S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers,” IEEE Trans. Comput., vol. 44, no. 2, pp. 223–233, Feb. 1995.

Digital Library

[20]

K. Ichino, T. Asakawa, S. Fukumoto, K. Iwasaki, and S. Kajihara, “Hybrid BIST using partially rotational scan,” in Proc. ATS, 2001, pp. 379–384.

[21]

A. Jas, C. V. Krishna, and N. A. Touba, “Hybrid BIST based on weighted pseudo-random testing: A new test resource partitioning scheme,” in Proc. VTS, 2001, pp. 2–8.

[22]

A. Jas, C. V. Krishna, and N. A. Touba, “Weighted pseudorandom hybrid BIST,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 12, pp. 1277–1283, Dec. 2004.

Digital Library

[23]

R. Kapur, S. Mitra, and T. W. Williams, “Historical perspective on scan compression,” IEEE Design Test, vol. 25, no. 2, pp. 114–120, Mar./Apr. 2008.

Digital Library

[24]

R. Kapur, S. Patil, T. J. Snethen, and T. W. Williams, “A weighted random pattern test generation system,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 8, pp. 1020–1025, Aug. 1996.

[25]

G. Kiefer, H. Vranken, E.-J. Marinissen, and H.-J. Wunderlich, “Application of deterministic logic BIST on industrial circuits,” in Proc. ITC, 2000, pp. 105–114.

[26]

B. Koenemann, “LFSR-coded test patterns for scan designs,” in Proc. ETC, 1991, pp. 237–242.

[27]

C. V. Krishna and N. A. Touba, “Reducing test data volume using LFSR reseeding with seed compression,” in Proc. ITC, 2002, pp. 321–330.

[28]

C. V. Krishna and N. A. Touba, “Hybrid BIST using an incrementally guided LFSR,” in Proc. Symp. Defect Fault Tolerance, 2003, pp. 217–224.

[29]

A. Kumar, J. Rajski, S. M. Reddy, and T. Rinderknecht, “On the generation of compact deterministic test sets for BIST ready designs,” in Proc. ATS, 2013, pp. 201–206.

[30]

J. Lee and N. A. Touba, “LFSR-reseeding scheme achieving low-power dissipation during test,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 2, pp. 396–401, Feb. 2007.

Digital Library

[31]

L. Lei and K. Chakrabarty, “Test set embedding for deterministic BIST using a reconfigurable interconnection network,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 9, pp. 1289–1305, Sep. 2004.

[32]

L. Lei and K. Chakrabarty, “Hybrid BIST based on repeating sequences and cluster analysis,” in Proc. DATE, 2005, pp. 1142–1147.

[33]

H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, “Two-dimensional test data compression for scan-based deterministic BIST,” in Proc. ITC, 2001, pp. 894–902.

[34]

Y. Liu, N. Mukherjee, J. Rajski, S. M. Reddy, and J. Tyszer, “Deterministic Stellar BIST for in-system automotive test,” in Proc. ITC, 2018, paper 13.2.

[35]

G. Mrugalski, J. Rajski, Ł. Rybak, J. Solecki, and J. Tyszer, “Star-EDT: Deterministic on-chip scheme using compressed test patterns,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 36, no. 4, pp. 683–693, Apr. 2017.

Digital Library

[36]

F. Muradali, V. K. Agarwal, and B. Nadeau-Dostie, “A new procedure for weighted random built-in self-test,” in Proc. ITC, 1990, pp. 660–669.

[37]

I. Pomeranz and S. M. Reddy, “3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 12, no. 7, pp. 1050–1058, Jul. 1993.

Digital Library

[38]

I. Pomeranz and S. M. Reddy, “Static test data volume reduction using complementation or modulo-M addition,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 6, pp. 1108–1112, Jun. 2011.

Digital Library

[39]

J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, “Embedded deterministic test,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 5, pp. 776–792, May 2004.

Digital Library

[40]

J. Rajski, J. Tyszer, G. Mrugalski, N. Mukherjee, W.-T. Cheng, and M. Kassab, “X-press: Two-stage X-tolerant compactor with programmable selector,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 7, no. 1, pp. 147–159, Jan. 2008.

[41]

J. Rajski, J. Tyszer, G. Mrugalski, and B. Nadeau-Dostie, “Test generator with preselected toggling for low power built-in self-test,” in Proc. VTS, 2012, pp. 1–6.

[42]

W. Rao, I. Bayraktaroglu, and A. Orailoglu, “Test application time and volume compression through seed overlapping,” in Proc. DAC, 2003, pp. 732–737.

[43]

P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici, “Low power mixed-mode BIST based on mask pattern generation using dual LFSR re-seeding,” in Proc. ICCD, 2002, pp. 474–479.

[44]

M. H. Schulz, E. Trischler, and T. M. Sarfert, “SOCRATES: A highly efficient automatic test pattern generation system,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 7, no. 1, pp. 126–137, Jan. 1988.

Digital Library

[45]

Y. Tanget al., “X-masking during logic BIST and its impact on defect coverage,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 2, pp. 193–202, Feb. 2006.

Digital Library

[46]

N. A. Touba, “Survey of test vector compression techniques,” IEEE Design Test, vol. 23, no. 4, pp. 294–303, Apr. 2006.

Digital Library

[47]

N. A. Touba and E. J. McCluskey, “Transformed pseudo-random patterns for BIST,” in Proc. VTS, 1995, pp. 410–416.

[48]

N. A. Touba and E. J. McCluskey, “Bit-fixing in pseudo-random sequences for scan BIST,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 4, pp. 545–555, Apr. 2001.

Digital Library

[49]

K.-H. Tsai, J. Rajski, and M. Marek-Sadowska, “Star test: The theory and its applications,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 9, pp. 1052–1064, Sep. 2000.

Digital Library

[50]

Z. Wang and K. Chakrabarty, “Test data compression for IP embedded cores using selective encoding of scan slices,” in Proc. ITC, 2005, pp. 581–590.

[51]

P. Wohl, J. A. Waicukauski, G. A. Maston, and J. E. Colburn, “XLBIST: X-tolerant logic BIST,” in Proc. ITC, 2018, paper 13.1.

[52]

P. Wohl, J. A. Waicukauski, S. Patel, and M. B. Amin, “X-tolerant compression and applications of scan-ATPG patterns in a BIST architecture,” in Proc. ITC, 2003, pp. 727–736.

[53]

P. Wohl, J. A. Waicukauski, S. Patel, F. DaSilva, T. W. Williams, and R. Kapur, “Efficient compression of deterministic patterns into multiple PRPG seeds,” in Proc. ITC, 2005, pp. 916–925.

[54]

H.-J. Wunderlich, “Multiple distributions for biased random test patterns,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 9, no. 6, pp. 584–593, Jun. 1990.

Digital Library

[55]

H.-J. Wunderlich and G. Kiefer, “Bit-flipping BIST,” in Proc. ICCAD, 1996, pp. 337–343.

[56]

H.-J. Wunderlich and G. Kiefer, “Deterministic BIST with multiple scan chains,” in Proc. ITC, 1998, pp. 1057–1064.

Cited By

Wang SZhou XHigami YTakahashi HIwata HMaeda YMatsushima J(2023)Test Point Insertion for Multi-Cycle Power-On Self-TestACM Transactions on Design Automation of Electronic Systems10.1145/356355228:3(1-21)Online publication date: 10-May-2023
https://dl.acm.org/doi/10.1145/3563552

Index Terms

Deterministic Stellar BIST for Automotive ICs
1. Information systems
  1. Data management systems
    1. Data structures
      1. Data layout

Index terms have been assigned to the content through auto-classification.

Recommendations

Digital Testing of ICs for Automotive Applications
VLSID '16: Proceedings of the 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)

The gradual change in consumer mindset from considering horsepower, style, and reliability as key factors when buying automobiles, to better energy efficiency, lower emissions, and advanced driver assistance systems (ADAS) is resulting in an exponential ...
Automotive Turing Test
PerMIS '07: Proceedings of the 2007 Workshop on Performance Metrics for Intelligent Systems

The Turing Test is often cited when the intelligence level of a presumably intelligent computer program is to be assessed. We propose to extend the scope of the test to the domain of intelligent automotive vehicles. We discuss possible formats for such ...
Preventing automotive pileup crashes in mixed-communication environments

Recent news illustrates the frequent occurrence of pileup crashes on highways. A predominant reason for the occurrence of such crashes is that current vehicles (including those equipped with an automatic cruise control system) do not provide drivers with ...

Comments

Information & Contributors

Information

Published In

cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 39, Issue 8

Aug. 2020

200 pages

ISSN:0278-0070

Issue’s Table of Contents

0278-0070 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See https://www.ieee.org/publications/rights/index.html for more information.

Publisher

IEEE Press

Publication History

Published: 01 August 2020

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Wang SZhou XHigami YTakahashi HIwata HMaeda YMatsushima J(2023)Test Point Insertion for Multi-Cycle Power-On Self-TestACM Transactions on Design Automation of Electronic Systems10.1145/356355228:3(1-21)Online publication date: 10-May-2023
https://dl.acm.org/doi/10.1145/3563552

View Options

View options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Issue’s Table of Contents