research-article

XPAND: An Efficient Test Stimulus Compression Technique

Authors:

Subhasish Mitra,

Kee Sup KimAuthors Info & Claims

IEEE Transactions on Computers, Volume 55, Issue 2

Pages 163 - 173

https://doi.org/10.1109/TC.2006.31

Published: 01 February 2006 Publication History

Abstract

Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from compressed seeds. Unlike major test compression techniques, this technique doesn't require test pattern generation with don't cares. Experimental results on industrial designs demonstrate that this new XPAND technique achieves exponential reduction in test data volume and test time compared to traditional scan and significantly outperforms existing test compression tools. The XPAND technique is currently being used by several industrial designs.

References

[1]

P.H. Bardell, W.H. McAnney, and J. Savir, Built-in Test for VLSI: Pseudo-Random Techniques. Wiley Inter-Science, 1987.

Digital Library

[2]

C. Barnhart, V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, and B. Koenemann, “OPMISR: The Foundation for Compressed ATPG Vectors,” Proc. Int'l Test Conf., pp. 748-757, 2001.

Digital Library

[3]

I. Bayraktaroglu and A. Orailoglu, “Test Volume and Application Time Reduction through Scan Chain Concealment,” Proc. Design Automation Conf., pp. 151-155, 2001.

Digital Library

[4]

I. Baryraktaroglu and A. Orailoglu, “Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression,” Proc. IEEE VLSI Test Symp., pp. 113-118, 2003.

Digital Library

[5]

N. Benowitz et al., “An Advanced Fault Isolation System for Digital Logic,” IEEE Trans. Computers, vol. 24, no. 5, pp. 489-497, May 1975.

Digital Library

[6]

A. Chandra, K. Chakrabarty, and R.A. Medina, “How Effective Are Compression Codes for Reducing Test Data Volume?” Proc. IEEE VLSI Test Symp., 2002.

Digital Library

[7]

I. Hamzaoglu and J.H. Patel, “Reducing Test Application Time for Full Scan Embedded Cores,” Proc. Int'l Symp. Fault-Tolerant Computing, pp. 260-267, 1999.

Digital Library

[8]

A. Jas, J. Ghosh-Dastidar, and N.A. Touba, “Scan Vector Compression/Decompression Using Statistical Coding,” Proc. IEEE VLSI Test Symp., pp. 114-120, 1999.

Digital Library

[9]

A. Khoche, E. Volkerink, J. Rivoir, and S. Mitra, “Test Vector Compression using ATE-DFT Synergies,” Proc. IEEE VLSI Test Symp., 2002.

Digital Library

[10]

B. Koenemann, “LFSR-Coded Test Patterns for Scan Designs,” Proc. European Test Conf., pp. 237-242, 1991.

[11]

B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, and D. Wheater, “A SmartBIST Variant with Guaranteed Encoding,” Proc. IEEE Asian Test Symp., pp. 325-330, 2001.

Digital Library

[12]

C.V. Krishna, A. Jas, and N.A. Touba, “Test Vector Encoding Using Partial LFSR Reseeding,” Proc. Int'l Test Conf., pp. 885-893, 2001.

Digital Library

[13]

K.J. Lee, J.J. Chen, and C.H. Huang, “Using a Single Input to Support Multiple Scan Chains,” Proc. Int'l Conf. Computer-Aided Design, pp. 74-78, 1998.

Digital Library

[14]

S. Lin and D.J. Costello, Error Control Coding: Fundamentals and Applications. Prentice Hall, 1983.

Digital Library

[15]

E.J. McCluskey, Logic Design Principles with Emphasis on Testable Semicustom Circuits. Englewood Cliffs, N.J.: Prentice Hall, 1986.

Digital Library

[16]

E.J. McCluskey, D. Burek, B. Koenemann, S. Mitra, J.H. Patel, J. Rajski, and J.A. Waicukauski, “Test Compression— Roundtable,” IEEE Design and Test of Computers, vol. 20, no. 2, pp. 76-87, Mar./Apr. 2003.

Digital Library

[17]

E.J. McCluskey et al., “ELF-MURPHY Data on Defects and Test Sets,” Proc. IEEE VLSI Test Symp., 2004.

Digital Library

[18]

S. Mitra and K.S. Kim, “X-Compact: Efficient Response Compaction for Test Cost Reduction,” Proc. Int'l Test Conf., 2002.

Digital Library

[19]

S. Mitra and K.S. Kim, “X-Compact: An Efficient Response Compaction Technique,” IEEE Trans. Computer-Aided Design, vol. 23, no. 3, pp. 421-432, Mar. 2004.

Digital Library

[20]

J. Rajski et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,” Proc. IEEE Int'l Test Conf., 2002.

Digital Library

[21]

T.R.N. Rao and E. Fujiwara, Error-Control Coding for Computer Systems. Prentice Hall, 1989.

Digital Library

[22]

S. Samaranayake, E. Gizdarski, N. Sitchinava, F. Neuveux, R. Kapur, and T.W. Williams, “A Reconfigurable Shared Scan-In Architecture,” Proc. IEEE VLSI Test Symp., pp. 9-14, 2003.

Digital Library

[23]

M.A. Shah and J.H. Patel, “Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs,” Proc. Int'l Symp. VLSI, pp. 167-172, 2004.

[24]

N. Sitchinava, S. Samaranayake, R. Kapur, E. Gizdarski, F. Neuveux, and T.W. Williams, “Changing the Scan Enable During Shift,” Proc. IEEE VLSI Test Symp., pp. 73-78, 2004.

Digital Library

[25]

N.A. Touba and E.J. McCluskey, “Bit Fixing in Pseudo Random Sequences for Scan BIST,” IEEE Trans. Computer-Aided Design, vol. 20, no. 4, pp. 545-555, Apr. 2001.

Digital Library

[26]

E.H. Volkerink, S. Mitra, and A. Khoche, “Packet Based Test Vector Compression Techniques,” Proc. Int'l Test Conf., 2002.

Digital Library

[27]

E.H. Volkerink and S. Mitra, “Efficient Seed Utilization for Reseeding Based Compression,” Proc. IEEE VLSI Test Symp., 2003.

Digital Library

[28]

L.T. Wang and E.J. McCluskey, “Circuits for Pseudoexhaustive Test Pattern Generation,” IEEE Trans. Computer-Aided Design, vol. 7, no. 10, pp. 1068-1080, Oct. 1988.

Digital Library

[29]

P. Wohl, J.A. Waicukauski, S. Patel, and M.B. Amin, “Efficient Compression and Application of Deterministic Patterns in a Logic BIST Architecture,” Proc. Design Automation Conf., pp. 566-569, 2003.

Digital Library

Cited By

Lee SRiener HMishchenko ABrayton RDe Micheli G(2022)A Simulation-Guided Paradigm for Logic Synthesis and VerificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310870441:8(2573-2586)Online publication date: 1-Aug-2022
https://dl.acm.org/doi/10.1109/TCAD.2021.3108704
Huhn SEggersglüß SChakrabarty KDrechsler R(2017)Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compressionProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130510(578-583)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130510
Gizdarski EWohl PWaicukauski J(2017)A New Paradigm for Synthesis of Linear DecompressorsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062190(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062190
Show More Cited By

Index Terms

XPAND: An Efficient Test Stimulus Compression Technique

Recommendations

Optimal choice of arithmetic compactors for mixed-signal systems
DFT '12: Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

Compaction circuits that have been used for mixed-signal systems testing constitute a part of encoding/decoding device for an arithmetic error-control code (ECC). These circuits are commonly referred to as residue computing circuits (RCCs). As ECCs ...
A diagnosis algorithm for extreme space compaction
DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

During volume testing, test application time, test data volume and high performance automatic test equipment (ATE) are the major cost factors. Embedded testing including built-in self-test (BIST) and multi-site testing are quite effective cost reduction ...
Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faults
DFT '12: Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

This paper describes an n-detection test generation strategy for mixed test sets, which consist of both broadside and skewed-load tests, targeting transition faults. The strategy consists of a test generation procedure without test compaction heuristics ...

Comments

Information & Contributors

Information

Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 55, Issue 2

February 2006

143 pages

ISSN:0018-9340

Issue’s Table of Contents

Copyright © 2006.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 February 2006

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

16
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Lee SRiener HMishchenko ABrayton RDe Micheli G(2022)A Simulation-Guided Paradigm for Logic Synthesis and VerificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310870441:8(2573-2586)Online publication date: 1-Aug-2022
https://dl.acm.org/doi/10.1109/TCAD.2021.3108704
Huhn SEggersglüß SChakrabarty KDrechsler R(2017)Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compressionProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130510(578-583)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130510
Gizdarski EWohl PWaicukauski J(2017)A New Paradigm for Synthesis of Linear DecompressorsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062190(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062190
Lee TTouba NYang J(2017)Enhancing Test Compression With Dependency Analysis for Multiple Expansion RatiosIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.268106336:9(1571-1579)Online publication date: 1-Sep-2017
https://dl.acm.org/doi/10.1109/TCAD.2017.2681063
Wei RKolovos DGarcia-Dominguez ABarmpis KPaige RBaudry BCombemale BKienzle JPretschner A(2016)Partial loading of XMI modelsProceedings of the ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems10.1145/2976767.2976787(329-339)Online publication date: 2-Oct-2016
https://dl.acm.org/doi/10.1145/2976767.2976787
Kumar AKassab MMoghaddam EMukherjee NRajski JReddy STyszer JChen Wang (2015)Isometric Test Data CompressionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.243213334:11(1847-1859)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1109/TCAD.2015.2432133
Gębala MMrugalski GMukherjee NRajski JTyszer J(2014)On Using Implied Values in EDT-based Test CompressionProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593173(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593173
Li JLiu XZhang YHu YLi XXu Q(2011)Capture-power-aware test data compression using selective encodingIntegration, the VLSI Journal10.1016/j.vlsi.2011.01.00544:3(205-216)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1016/j.vlsi.2011.01.005
Rabenalt TGoessel MLeininger A(2011)Masking of X-Values by Use of a Hierarchically Configurable RegisterJournal of Electronic Testing: Theory and Applications10.1007/s10836-010-5179-227:1(31-41)Online publication date: 1-Feb-2011
https://dl.acm.org/doi/10.1007/s10836-010-5179-2
Wang ZChakrabarty KWang S(2009)Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202173128:8(1251-1264)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2021731
Show More Cited By

View Options

View options

Media

Figures

Other

Tables

View Issue’s Table of Contents