Article

Efficient Seed Utilization for Reseeding based Compression

Authors:

Erik H. Volkerink,

Subhasish MitraAuthors Info & Claims

VTS '03: Proceedings of the 21st IEEE VLSI Test Symposium

Page 232

Published: 27 April 2003 Publication History

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Abstract

The conventional LFSR reseeding technique for test datacompression generates one test pattern from each LFSRseed. The seed size is determined by the maximumnumber of specified bits in a test pattern belonging to agiven test set. However, for most practical designs themajority of test patterns have significantly fewerspecified bits compared to the maximum. This limits theamount of compression that can be achieved withconventional reseeding. This paper presents a newreseeding technique that overcomes this problem bygenerating a single test pattern from multiple seeds andmultiple test patterns from a single seed. The newreseeding technique is applied to two industrial designsresulting in significant reduction in tester memoryrequirement and test application time compared to theconventional reseeding technique.

Cited By

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Gizdarski EWohl PWaicukauski J(2017)A New Paradigm for Synthesis of Linear DecompressorsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062190(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062190
Karmakar RChattopadhyay S(2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.002
Li JLiu XZhang YHu YLi XXu Q(2011)Capture-power-aware test data compression using selective encodingIntegration, the VLSI Journal10.1016/j.vlsi.2011.01.00544:3(205-216)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1016/j.vlsi.2011.01.005
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Index Terms

Efficient Seed Utilization for Reseeding based Compression
1. Hardware
2. Information systems
  1. Data management systems
    1. Data structures
      1. Data layout
        Data compression

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VTS '03: Proceedings of the 21st IEEE VLSI Test Symposium

April 2003

ISBN:0769519245

Publisher

IEEE Computer Society

United States

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Published: 27 April 2003

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Cited By

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Gizdarski EWohl PWaicukauski J(2017)A New Paradigm for Synthesis of Linear DecompressorsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062190(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062190
Karmakar RChattopadhyay S(2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.002
Li JLiu XZhang YHu YLi XXu Q(2011)Capture-power-aware test data compression using selective encodingIntegration, the VLSI Journal10.1016/j.vlsi.2011.01.00544:3(205-216)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1016/j.vlsi.2011.01.005
Lee JTouba N(2010)Correlation-based rectangular encodingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202588218:10(1483-1492)Online publication date: 1-Oct-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2025882
Koutsoupia MKalligeros EKavousianos XNikolos DBenini LDe Micheli GAl-Hashimi BMueller W(2009)LFSR-based test-data compression with self-stoppable seedsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874975(1482-1487)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874975
Wang ZChakrabarty KWang S(2009)Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202173128:8(1251-1264)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2021731
Wang ZFang HChakrabarty KBienek M(2009)Deviation-based LFSR reseeding for test-data compressionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200916628:2(259-271)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1109/TCAD.2008.2009166
Tenentes VKavousianos XKalligeros ESciuto D(2008)State skip LFSRsProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403488(474-479)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403488
Kavousianos XKalligeros ENikolos D(2008)Multilevel-Huffman test-data compression for IP cores with multiple scan chainsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200044816:7(926-931)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.2000448
Wang ZChakrabarty KWang SLauwereins RMadsen J(2007)SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test schedulingProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266410(201-206)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266410
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