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Deviation-based LFSR reseeding for test-data compression

Published: 01 February 2009 Publication History

Abstract

Linear feedback shift register (LFSR) reseeding forms the basis for many test-compression solutions. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. Despite the availability of numerous LFSR-reseeding-based compression methods in the literature, relatively little is known about the effectiveness of these seeds for unmodeled defects, particularly since there are often several candidate seeds for a test cube. We use the recently proposed output deviation measure of the resulting patterns as a metric to select appropriate LFSR seeds. Experimental results are reported using test patterns for stuck-at and transition faults derived from selected seeds for the ISCAS-89 and the IWLS-05 benchmark circuits. These patterns achieve higher coverage for transition and stuck-open faults than patterns obtained using other seed-generation methods for LFSR reseeding. Given a pattern pair (p1, p2) for transition faults, we also examine the transition-fault coverage for launch on capture by using p1 and p2 to separately compute output deviations. Results show that p1 tends to be better when there is a high proportion of do-not-care bits in the test cubes, while p2 is a more appropriate choice when the transition-fault coverage is high.

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  • (2016)Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data CompressionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.241341635:2(274-284)Online publication date: 18-Jan-2016
  • (2016)On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern GenerationIEEE Transactions on Computers10.1109/TC.2015.242869765:2(664-669)Online publication date: 1-Feb-2016
  • (2014)Low-power selective pattern compression for scan-based test applicationsComputers and Electrical Engineering10.1016/j.compeleceng.2013.11.02840:4(1053-1063)Online publication date: 1-May-2014
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Published In

cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 28, Issue 2
February 2009
138 pages

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IEEE Press

Publication History

Published: 01 February 2009
Revised: 16 August 2008
Received: 16 May 2008

Author Tags

  1. Defect coverage
  2. defect coverage
  3. linear feedback shift register (LFSR) reseeding
  4. output deviation
  5. seed selection
  6. test compression

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View all
  • (2016)Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data CompressionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.241341635:2(274-284)Online publication date: 18-Jan-2016
  • (2016)On The Computation of LFSR Characteristic Polynomials for Built-In Deterministic Test Pattern GenerationIEEE Transactions on Computers10.1109/TC.2015.242869765:2(664-669)Online publication date: 1-Feb-2016
  • (2014)Low-power selective pattern compression for scan-based test applicationsComputers and Electrical Engineering10.1016/j.compeleceng.2013.11.02840:4(1053-1063)Online publication date: 1-May-2014
  • (2012)Functional test-sequence grading at register-transfer levelIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.216365120:10(1890-1894)Online publication date: 1-Oct-2012
  • (2010)Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test GenerationJournal of Electronic Testing: Theory and Applications10.1007/s10836-010-5142-226:2(165-176)Online publication date: 1-Apr-2010
  • (2010)RTL DFT Techniques to Enhance Defect Coverage for Functional Test SequencesJournal of Electronic Testing: Theory and Applications10.1007/s10836-009-5135-126:2(151-164)Online publication date: 1-Apr-2010

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